Low Power Filtering Techniques for wideband and wireless applications

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Low Power Filtering Techniques for wideband and wireless applications

A Dissertation
by
MANISHA GAMBHIR
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
August 2009
Major Subject: Electrical Engineering
LOW POWER FILTERING TECHNIQUES FOR WIDEBAND AND WIRELESS
APPLICATIONS
A Dissertation
by
MANISHA GAMBHIR
Submitted to the Office of Graduate Studies of
Texas A&M University
in partial fulfillment of the requirements for the degree of
DOCTOR OF PHILOSOPHY
Approved by:
Co-Chairs of Committee, Edgar Sanchez-Sinencio
Jose Silva-Martinez
Committee Members, Shankar P. Bhattacharyya
Alexander G. Parlos
Head of Department, Costas N. Georghiades
August 2009
Major Subject: Electrical Engineering
iii
ABSTRACT
Low Power Filtering Techniques for Wideband and Wireless Applications.
(August 2009)
Manisha Gambhir, B.E., Delhi University, India;
M.S., Texas A&M University, College Station
Co-Chairs of Advisory Committee: Dr. Edgar Sanchez-Sinencio
Dr. Jose Silva-Martinez
This dissertation presents design and implementation of continuous time analog
filters for two specific applications: wideband analog systems such as disk drive channel
and low-power wireless applications. Specific focus has been techniques that reduce the
power requirements of the overall system either through improvement in architecture or
efficiency of the analog building blocks.
The first problem that this dissertation addresses is the implementation of
wideband filters with high equalization gain. An efficient architecture that realizes
equalization zeros by combining available transfer functions associated with a
biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with
24dB boost is designed using the proposed architecture. The prototype fabricated in
standard 0.35μm CMOS process shows -41dB of IM3 for 250mV peak to peak swing
with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using
similar architecture is discussed in brief. It is shown that, for practical range of
iv
frequency and SNR, LC based design is more power efficient than a Gm-C one, though
at the cost of much larger area.
Secondly, a complementary current mirror based building block is proposed,
which pushes the limits imposed by conventional transconductors on the powerefficiency
of Gm-C filters. Signal processing through complementary devices provides
good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly
7 times. A current-mode 4th order Butterworth filter is designed, in 0.13μm UMC
technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in
1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter
realization occupies a relatively small area and is well suited for integration in deep
submicron technologies.
Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter
is designed for a ten bit continuous time sigma delta ADC architecture developed
specifically for fine-line CMOS technologies. Inverter based amplification and a
common mode feedback for such amplifiers are discussed. The filter consumes 5mW of
power and occupies an area of 0.07 mm2.

TABLE OF CONTENTS
Page
ABSTRACT......................................................................................................................iii
DEDICATION...................................................................................................................iv
ACKNOWLEDGEMENTS................................................................................................v
TABLE OF CONTENTS..................................................................................................vi
LIST OF FIGURES.........................................................................................................viii
LIST OF TABLES...........................................................................................................xii
1. INTRODUCTION........................................................................................................1
1.1. Motivation.............................................................................................................1
1.2. Overview of analog filters.....................................................................................3
1.2.1. Discrete-time filters....................................................................................4
1.2.2. Continuous-time filters...............................................................................5
1.3. Overview of analog-to-digital converter architectures.........................................6
1.4. Organization of the thesis.....................................................................................7
2. PROPERTIES OF THE SIGMA-DELTA MODULATOR.........................................9
2.1. Analog-to-digital conversion............................................................................... 9
2.2. Ideal sigma-delta modulator...............................................................................11
2.3. Continuous-time and discrete-time sigma-delta modulators..............................13
2.4. Non-idealities in continuous-time sigma-delta modulators................................16
2.4.1. Circuit noise..............................................................................................16
2.4.2. Non-linearity.............................................................................................17
2.4.3. Component mismatches............................................................................18
2.4.4. Excess loop delay.....................................................................................18
2.4.5. Clock jitter................................................................................................19
2.5. Performance parameters of sigma-delta modulators..........................................21
2.5.1. Signal-to-noise-and-distortion ratio (SNDR)...........................................21
2.5.2. Dynamic range (DR).................................................................................21
3. DESIGN OF CONTINUOUS-TIME SIGMA-DELTA MODULATOR...................22
3.1. Introduction........................................................................................................22
3.2. Loop filter transfer function...............................................................................23
3.3. Modulator loop topology....................................................................................25
3.4. Overview of system implementation..................................................................27
3.5. Behavioral simulations of the system.................................................................29
4. DESIGN OF Gm-C BIQUADRATIC FILTER..........................................................31
vii
Page
4.1. Gm-C integrator...................................................................................................31
4.2. OTA architecture................................................................................................33
4.2.1. Noise analysis of Gm-C-OTA integrator...................................................35
4.2.2. Linearity analysis of Gm-C-OTA..............................................................37
4.2.3. OTA simulation results.............................................................................38
4.3. The Gm-C biquadratic cell..................................................................................41
4.3.1. Linearity analysis of the Gm-C biquad......................................................42
4.3.2. Noise analysis of the Gm-C biquad...........................................................50
4.4. Biquad simulation results...................................................................................52
5. DESIGN OF A 5TH ORDER ACTIVE-RC LOW-PASS FILTER.............................56
5.1. Introduction........................................................................................................56
5.1.1. Architectural considerations.....................................................................57
5.1.2. Design considerations...............................................................................58
5.2. Design of amplifier..............................................................................................59
5.2.1. Amplifier architecture...............................................................................60
5.2.2. Amplifier circuit implementation.............................................................62
5.2.3. Simulation results of the amplifier...........................................................64
5.3. Second order filter realization.............................................................................68
5.3.1. Design considerations...............................................................................68
5.4. First-order integrator stage..................................................................................74
5.5. Summing amplifier..............................................................................................76
5.5.1. Stability considerations.............................................................................77
5.5.2. Summing amplifier design requirements..................................................79
5.5.3. Optimizing for group delay......................................................................83
5.5.4. Circuit implementation of summing amplifier.........................................88
5.5.5. Summing amplifier simulation results......................................................90
6. RESULTS...................................................................................................................92
6.1. Preliminary experimental results of CT LP ΣΔ ADC.........................................92
6.2. Simulation results for the 5th order low-pass filter..............................................95
6.2.1. Simulation results for first stage of filter.................................................96
6.2.2. Simulation results for second stage of filter..........................................100
6.2.3. Simulation results for third stage of filter..............................................102
7. SUMMARY AND CONCLUSIONS.......................................................................104
REFERENCES...............................................................................................................106
VITA..............................................................................................................................109

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