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module StructuralAccumulator(
Clock,
ClockEnable,
Reset,
Set,
//------------------------------------------------------------------
//------------------------------------------------------------------
// Input Interface
//------------------------------------------------------------------
A,
ALUOp,
//------------------------------------------------------------------
//------------------------------------------------------------------
// Output Interface
//------------------------------------------------------------------
Result
//------------------------------------------------------------------
);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 1;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Clock and Reset Inputs
//--------------------------------------------------------------------------
input wire Clock, ClockEnable, Reset, Set;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Inputs
//--------------------------------------------------------------------------
input wire [Width-1:0] A;
input [2:0] ALUOp;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Outputs
//--------------------------------------------------------------------------
output wire [Width-1:0] Result;
//--------------------------------------------------------------------------
wire [Width-1:0] aluout;
genvar i;
generate for (i=0; i < Width; i=i+1)
begin: bit
FDRSE #(
.INIT(1'b0) // Initial value of register (1’b0 or 1’b1)
) FDRSE_inst (
.Q(Result[i]), // Data output
.C(Clock), // Clock input
.CE(ClockEnable), // Clock enable input
.D(aluout[i]), // Data input
.R(Reset), // Synchronous reset input
.S(Set) // Synchronous set input
);
case(ALUOp)
3'b000: assign aluout[i] = A[i] + Result[i];
3'b001: assign aluout[i] = A[i] - Result[i];
3'b010: assign aluout[i] = A[i] & Result[i];
3'b011: assign aluout[i] = A[i] | Result[i];
3'b100: assign aluout[i] = A[i] ^ Result[i];
3'b101: assign aluout[i] = ~A[i];
3'b110: assign aluout[i] = A[i];
default: assign aluout[i] = A[i];
endcase
end
endgenerate
//--------------------------------------------------------------------------
endmodule
最终,程序总是显示在 case(ALUOp)里显示Illegal expression in generate case statement。不知道如何解决,另外,generate应该如何是使用,谢谢。 |
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