贡献一片09年fractionN PLL的PHD论文

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This work presents two novel phase lock loop (PLL) architectures in order to minimize the quantization noise leakage in wideband Delta-Sigma fractional-N synthesizers. The first approach presents a 6GHz Type-I fractional-N PLL with a noise-cancelling discrete-time sample-and-hold loop-filter for Worldwide Inter-operability for Microwave Access (WiMAX) application. The 1MHz bandwidth PLL utilizes an inherently linear phase frequency detector (PFD) and noise cancelling charge-pump (CP) digital-to-Analog converter (DAC) circuit to reduce quantization noise by more than 20dB.;The overall results are as follows: The measured in-band phase noise at 300kHz offset from the 6.12GHz carrier is -100dBc/Hz and out-of-band phase noise is -130dBc/Hz at 3MHz offset. The root mean square (RMS) phase error integrated from 1kHz-10MHz is calculated at -42 dBc. A sweep of near integer spurs shows a worst case in-band spur measurement of -61dBc at 130.5kHz offset. The reference spur is measured at -79dBc. The PLL loop settling time for an accuracy of 0.01 part per million (ppm) and a frequency step of 60 MHz is less than 11 micro seconds.;The second design presents a 3GHz wideband Delta-Sigma fractional- N synthesizer with an exponential settling voltage-mode PFD. The 1MHz bandwidth Type-I PLL loop utilizes the exponential small-signal settling characteristics of a voltage-mode N-type metal oxide semiconductor (NMOS) follower low-dropout regulator (LDO) base PFD-CP to reduce in-band quantization noise leakage by 15dB without the need for noise suppression DAC. The traditional tri-state CP-PFD is replaced with a voltage-mode passive resistor capacitor (RC) charge-pump, where the quantization noise generated by the Delta-Sigma digital modulator is attached to the trailing edge of the phase error at the output of the PFD, being suppressed by the exponentially decaying characteristic of the CP.;The overall results for the 3GHz PLL are as follows: With less than 20 miliampers current consumption from 1.8 volts power supply, the measured in-band phase noise at 100 kHz is -107dBc/Hz and out-of-band phase noise at 3 MHz is -130dBc/Hz. The PLL loop settling time for an accuracy of 0.1ppm and a frequency step of 45 MHz is less than 10 micro seconds.

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WIDEBAND FREQUENCY SYNTHESIZERS FOR FUTURE WIRELESS COMMUNICATION SYSTEMS
   
by Hedayati, Hiva, Ph.D., ARIZONA STATE UNIVERSITY, 2009, 96 pages;

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bilinzhuxiao

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