IC Compiler 2009.06 workshop(PDF)+LAB数据文件-应该是目前最新的ICC的WORKSHOP

zheng070608138 · 发表于 2013-9-9 15:19:06

第三个文件是骗人的吧，明明是lab，却说是workshop

sathya · 发表于 2013-9-13 01:40:36

Post CTS: Uncertainty will be decreased in SDC. Clock skew (including the OCV) target will be
given in ctstch.
eg:A 1 ns clock with a 100 ps clock uncertainty means that the next clock tick will arrive in 1 ns
plus or minus 50 ps.
Setup uncertainty should include all of them (capture clock and launch clock are different) but
we can ignore PLL jitter in hold uncertainty (capture clock and launch clock are same), and OCV
uncertainty for hold can be less than setup.