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本帖最后由 shaweikang1984 于 2011-1-30 11:01 编辑
Abstract
In this paper, we propose a new circuit technique for
on-chip communication, the edge encoding technique, to reduce
the energy consumption in multi-cycle interconnects. Both average
and worst-case energy are reduced by desynchronizing the edges of
rising and falling transitions. In a 1.2 V 65-nm CMOS technology,
the proposed approach achieves up to 34% energy reduction with
no latency overhead over optimally designed conventional busses
due to coupling capacitance reductions. The technique further reduces
energy consumption by 39% with iso-throughput at the expense
of one-cycle latency. Energy savings are shown to be both
larger and more robust to process, voltage, and temperature variations
than previous techniques.
05286242.pdf
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