Verificatiom Methodology Manual for System Verilog

ktzhan

The VMM for SystemVerilog is our recommended reference book to architect SystemVerilog verification environments. It defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality, and will complement the IP Functional Verification Guide being developed by the STARC IP Reuse Engineering Group.

Verificatiom_Methodology_Manual_for_System_Verilog.pdf (4.22 MB, 下载次数: 29 )

2011-1-17 11:29 上传

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imiori

感谢分享

zh123456789

别人发过的啊

mtwumtwu

good reference for verilog design

fixit

thanks for sharing

cool88now

非常感谢。。

alone_2

感谢上苍 。

alone_2

这书好么？？？？

adeux2000

good!!

j1629

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