Verificatiom Methodology Manual for System Verilog

ktzhan · 发表于 2011-1-17 11:30:55

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The VMM for SystemVerilog is our recommended reference book to architect SystemVerilog verification environments. It defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality, and will complement the IP Functional Verification Guide being developed by the STARC IP Reuse Engineering Group.

Verificatiom_Methodology_Manual_for_System_Verilog.pdf (4.22 MB, 下载次数: 29 )

imiori · 发表于 2011-1-17 11:52:47

感谢分享

zh123456789 · 发表于 2011-1-17 12:55:13

别人发过的啊

mtwumtwu · 发表于 2011-1-17 13:29:04

good reference for verilog design

fixit · 发表于 2011-1-17 20:00:11

thanks for sharing

cool88now · 发表于 2011-3-3 17:31:13

非常感谢。。

alone_2 · 发表于 2011-3-3 20:07:26

感谢上苍。

alone_2 · 发表于 2011-3-3 20:13:12

这书好么？？？？

adeux2000 · 发表于 2011-3-4 15:54:27

good!!

j1629 · 发表于 2011-3-5 05:29:17

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[资料] Verificatiom Methodology Manual for System Verilog

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