我做了一个数据采集、USB传输系统，编译后所占逻辑资料才1%？请高手帮忙看看，谢谢！

melinda

感觉系统挺大的，有七个小模块。
编译完后所占资源太少，感觉有问题，但不知出在哪里，请高手帮忙看看。非常感谢！

综合编译结果

以下是warnings:
Warning (10261): Verilog HDL Event Control warning at ad9224.v(38): Event Control contains a complex event expression
Warning (10272): Verilog HDL Case Statement warning at autoshift.v(29): case item expression covers a value already covered by a previous case item
Warning (10240): Verilog HDL Always Construct warning at autoshift.v(24): inferring latch(es) for variable "multi_in", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at autoshift.v(24): inferring latch(es) for variable "da_in", which holds its previous value in one or more paths through the always construct
Warning (10235): Verilog HDL Always Construct warning at usb.v(64): variable "SLWR" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(65): variable "SLWR" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(69): variable "SLRD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at usb.v(77): variable "SLRD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10272): Verilog HDL Case Statement warning at usb.v(76): case item expression covers a value already covered by a previous case item
Warning (10230): Verilog HDL assignment warning at usb.v(99): truncated value with size 32 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(117): variable "FD" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(116): truncated value with size 32 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(139): variable "fromFIFO0" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(138): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at usb.v(159): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at usb.v(163): truncated value with size 10 to match size of target (8)
Warning (10235): Verilog HDL Always Construct warning at usb.v(172): variable "fromFIFO1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at usb.v(171): truncated value with size 32 to match size of target (8)
Warning (10272): Verilog HDL Case Statement warning at usb.v(166): case item expression covers a value already covered by a previous case item
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "EP2FULL", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "FIFOADR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "SLWR", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "SLRD", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "wrreq1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "toFIFO1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "rdreq0", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "FD", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "EP6EMPT", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "ad_cs", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "SLOE", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "wrreq0", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "PKEND", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at usb.v(83): inferring latch(es) for variable "rdreq1", which holds its previous value in one or more paths through the always construct
Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: altpll0
Warning: Using design file fifo1.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: fifo1
Warning: The following nodes have both tri-state and non-tri-state drivers
Warning: Inserted always-enabled tri-state buffer between "FD[11]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[10]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[9]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[8]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[7]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[6]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[5]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[4]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[3]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[2]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[1]" and its non-tri-state driver.
Warning: Inserted always-enabled tri-state buffer between "FD[0]" and its non-tri-state driver.
Warning: The following tri-state nodes are fed by constants
Warning: The pin "FD[15]" is fed by GND
Warning: The pin "FD[14]" is fed by GND
Warning: The pin "FD[13]" is fed by GND
Warning: The pin "FD[12]" is fed by GND
Warning: Latch autoshift:inst3|da_in[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[1]
Warning: Latch autoshift:inst3|da_in[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[1]
Warning: Latch autoshift:inst3|da_in[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[0]
Warning: Latch autoshift:inst3|multi_in[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[0]
Warning: Latch autoshift:inst3|multi_in[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[1]
Warning: Latch autoshift:inst3|multi_in[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[3]
Warning: TRI or OPNDRN buffers permanently enabled
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Node "FD~synth"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "da_cs" is stuck at VCC
Warning (13410): Pin "da_wr" is stuck at VCC
Warning (13410): Pin "full" is stuck at VCC
Warning (13410): Pin "empty" is stuck at GND
Warning (13410): Pin "PKEND" is stuck at GND
Warning (13410): Pin "SLOE" is stuck at GND
Warning (13410): Pin "da_in[7]" is stuck at VCC
Warning (13410): Pin "da_in[6]" is stuck at VCC
Warning (13410): Pin "da_in[5]" is stuck at VCC
Warning (13410): Pin "da_in[4]" is stuck at VCC
Warning (13410): Pin "da_in[0]" is stuck at GND
Warning (13410): Pin "FIFOADR[0]" is stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "msb"
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "IFCLK" is assigned to location or region, but does not exist in design
Warning: Node "ad_clk" is assigned to location or region, but does not exist in design
Warning: Node "sht[0]" is assigned to location or region, but does not exist in design
Warning: Node "sht[1]" is assigned to location or region, but does not exist in design
Warning: Node "sht[2]" is assigned to location or region, but does not exist in design
Warning: Node "sht[3]" is assigned to location or region, but does not exist in design
Warning: Found 39 output pins without output pin load capacitance assignment
Info: Pin "FD[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FD[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_cs" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_wr" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "full" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "empty" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "PKEND" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLWR" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLRD" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "SLOE" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "EP6EMPT" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "EP2FULL" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "da_in[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FIFOADR[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "FIFOADR[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "multi_in[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Warning: Following 16 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info: Pin FD[15] has a permanently enabled output enable
Info: Pin FD[14] has a permanently enabled output enable
Info: Pin FD[13] has a permanently enabled output enable
Info: Pin FD[12] has a permanently enabled output enable
Info: Pin FD[11] has a permanently enabled output enable
Info: Pin FD[10] has a permanently enabled output enable
Info: Pin FD[9] has a permanently enabled output enable
Info: Pin FD[8] has a permanently enabled output enable
Info: Pin FD[7] has a permanently enabled output enable
Info: Pin FD[6] has a permanently enabled output enable
Info: Pin FD[5] has a permanently enabled output enable
Info: Pin FD[4] has a permanently enabled output enable
Info: Pin FD[3] has a permanently enabled output enable
Info: Pin FD[2] has a permanently enabled output enable
Info: Pin FD[1] has a permanently enabled output enable
Info: Pin FD[0] has a permanently enabled output enable
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "USB:inst5|toFIFO1[0]" is a latch
Warning: Node "USB:inst5|toFIFO1[1]" is a latch
Warning: Node "USB:inst5|toFIFO1[2]" is a latch
Warning: Node "USB:inst5|toFIFO1[3]" is a latch
Warning: Node "USB:inst5|FD[0]$latch" is a latch
Warning: Node "USB:inst5|FD[1]$latch" is a latch
Warning: Node "USB:inst5|FD[2]$latch" is a latch
Warning: Node "USB:inst5|FD[3]$latch" is a latch
Warning: Node "USB:inst5|EP2FULL" is a latch
Warning: Node "USB:inst5|SLRD" is a latch
Warning: Node "USB:inst5|EP6EMPT" is a latch
Warning: Node "USB:inst5|SLWR" is a latch
Warning: Node "autoshift:inst3|da_in[3]" is a latch
Warning: Node "autoshift:inst3|da_in[2]" is a latch
Warning: Node "autoshift:inst3|da_in[1]" is a latch
Warning: Node "autoshift:inst3|multi_in[2]" is a latch
Warning: Node "autoshift:inst3|multi_in[1]" is a latch
Warning: Node "autoshift:inst3|multi_in[0]" is a latch
Warning: Node "USB:inst5|FD[11]$latch" is a latch
Warning: Node "USB:inst5|FD[10]$latch" is a latch
Warning: Node "USB:inst5|FD[9]$latch" is a latch
Warning: Node "USB:inst5|FD[8]$latch" is a latch
Warning: Node "USB:inst5|FD[7]$latch" is a latch
Warning: Node "USB:inst5|FD[6]$latch" is a latch
Warning: Node "USB:inst5|FD[5]$latch" is a latch
Warning: Node "USB:inst5|FD[4]$latch" is a latch
Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Found 20 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "USB:inst5|always2~3" as buffer
Info: Detected gated clock "USB:inst5|WideOr0" as buffer
Info: Detected ripple clock "USB:inst5|state.state3" as buffer
Info: Detected ripple clock "USB:inst5|state.state0" as buffer
Info: Detected ripple clock "USB:inst5|state.state2" as buffer
Info: Detected ripple clock "USB:inst5|state.state1" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg9" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg8" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg7" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg6" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg5" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg4" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg3" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg2" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg1" as buffer
Info: Detected ripple clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|ram_block3a0~porta_address_reg0" as buffer
Info: Detected gated clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[3]" as buffer
Info: Detected gated clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[2]" as buffer
Info: Detected gated clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[1]" as buffer
Info: Detected gated clock "fifo1:inst1|scfifo:scfifo_component|scfifo_gt21:auto_generated|a_dpfifo_n331:dpfifo|dpram_5v01:FIFOram|altsyncram_iuj1:altsyncram1|altsyncram_koc1:altsyncram2|q_a[0]" as buffer
Warning: Can't achieve minimum setup and hold requirement altpll0:inst8|altpll:altpll_component|_clk0 along 2 path(s). See Report window for details.

liqz

哥们你这问题也太多了吧，latch必须解决掉，PIN管教是不是没连？

liqz

建议你一个一个warning的解决

melinda

如何解决LATCH？

liqz

把if else写完整

ahhfyz

写完整

melinda

是的，我肯定有考虑不周的地方，急切地想实现先。warning也应该一个一个解决！

xiaochen19

最近在学USB,楼主能不能把源程序共享下？感激不尽啊！

CoCo3646

Synthesis Result has Latch,It will cause U design damage(Some time can run, Some time can not)
It say that U rtl has problem
for example
case x[2:0]
0 : y=1;
1 : y=2;
endcase
y will be latch(because U do'nt let Synthesis tool know that when x=2/3/4/5/6/7, -->y=?
so that generate internal Latch in U ckt,It cause un-know Timing problem in U ckt