Warning: A non-unate path in clock network(TIM-052)

madoka28

if clk source is generate clock + combination logic
   for instance
   always@(clkc, reset) ....
   1. clkc= (reg0_bit0 ^ clkb) ->  reg_bot0 xor clkb  
   2. clkb = clka/2 (generated form clka)
   3. source clk  =  clka
   it sould be always ( clkb ,...)
   then dc can recongnize clkb is generate from clka
   but
   add reg0_bit0 just want to control  DFF clkc = posedge clkb  or negedge clkb
   Q :
    how  to add dc constrain to inform DC about the design we want to do  ?

jcchan

Positive unate means the output rising due to the input rising,the output falling due to the input falling. Negative unate means the output rising due to the input falling,the output falling due to the input rising.Non unate means the output rising due to the input rising or falling, the output falling also due to the input rising or falling.