时序错误

liuxiantao11 · 发表于 2010-8-26 17:17:49

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我发现综合后时序错误，可是不知道怎么改

liuxiantao11 · 发表于 2010-8-26 17:33:38

特此请教！

yemifeng · 发表于 2010-8-26 19:17:31

第一步，有没有添加时序约束，如果没有，添加了再看结果

如果添加了还是不行，则要看约束是不是添过了头，比如说你实际上时钟只要50M就可以了，但你约束了100M,这时应该减轻约束，再看结果

如果还是不行，可以查看时序分析报告，查看最差的路径，看哪个不符合时序，然后修改代码，比如纯组合逻辑延时太长，那么是否可以在中间加一个寄存器平横一下

我会的就那么多了，要是再让我不行的话，我就要大改代码了，呵呵

liuxiantao11 · 发表于 2010-8-26 19:27:15

我用synplify综合的，我看时钟周期是有约束的，我也看到时序报告中的错误，可是不知道怎么改

liuxiantao11 · 发表于 2010-8-26 19:29:21

Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 8.307 ns HIGH 50%;

559655 paths analyzed, 6537 endpoints analyzed, 66 failing endpoints
66 timing errors detected. (66 setup errors, 0 hold errors)
Minimum period is 9.716ns.
--------------------------------------------------------------------------------
Slack:                -1.409ns (requirement - (data path - clock path skew + uncertainty))
  Source:             posi_q5[4] (FF)
  Destination:       data_deintlv[4] (FF)
  Requirement:       8.307ns
  Data Path Delay:    9.431ns (Levels of Logic = 12)
  Clock Path Skew:    -0.285ns (2.375 - 2.660)
  Source Clock:       clk_c rising at 0.000ns
  Destination Clock: clk_c rising at 8.307ns
  Clock Uncertainty: 0.000ns

  Maximum Data Path: posi_q5[4] to data_deintlv[4]
Location          Delay type       Delay(ns)  Physical Resource
                                                   Logical Resource(s)
-------------------------------------------------  -------------------
SLICE_X105Y136.YQ Tcko                0.374 posi_q5[5]
                                                   posi_q5[4]
SLICE_X104Y138.F4 net (fanout=2)       0.324 posi_q5[4]
SLICE_X104Y138.COUT  Topcyf             0.744 un1_posi_q5_1_s_4
                                                   un1_posi_q5_1_s_4_sf
                                                   un1_posi_q5_1_cry_4
                                                   un1_posi_q5_1_cry_5
SLICE_X104Y139.CIN net (fanout=1)       0.000 un1_posi_q5_1_cry_5/O
SLICE_X104Y139.Y    Tciny                0.891 un1_posi_q5_1_s_6
                                                   un1_posi_q5_1_cry_6
                                                   un1_posi_q5_1_s_7
SLICE_X106Y137.G3 net (fanout=2)       0.468 un1_posi_q5_1_s_7
SLICE_X106Y137.COUT  Topcyg             0.645 un1_posi_q5_2_0.I_28/O
                                                   un1_posi_q5_2_0.I_36
                                                   un1_posi_q5_2_0.I_28
SLICE_X106Y138.CIN net (fanout=1)       0.000 un1_posi_q5_2_0.I_28/O
SLICE_X106Y138.XB Tcinxb             0.514 I_37_6
                                                   un1_posi_q5_2_0.I_37
SLICE_X106Y124.F4 net (fanout=1)       0.799 I_37_6
SLICE_X106Y124.X    Tilo                0.288 un1_posi_q1_3_0
                                                   un1_posi_q1_3_0
SLICE_X102Y125.F4 net (fanout=1)       0.290 un1_posi_q1_3_0
SLICE_X102Y125.X    Tilo                0.288 N_3524
                                                   un1_posi_q1_3
SLICE_X96Y111.F4    net (fanout=10)    1.045 N_3524
SLICE_X96Y111.X    Tilo                0.288 data_deintlv_0_sqmuxa_1
                                                   data_deintlv_0_sqmuxa_1_0_a2
SLICE_X99Y110.F3    net (fanout=3)       0.279 data_deintlv_0_sqmuxa_1
SLICE_X99Y110.X    Tilo                0.288 data_deintlv_4_sqmuxa_1
                                                   data_deintlv_4_sqmuxa_1
SLICE_X97Y110.G3    net (fanout=3)       0.272 data_deintlv_4_sqmuxa_1
SLICE_X97Y110.Y    Tilo                0.313 data_deintlv_30_1_1_1_0[4]
                                                   data_deintlv_30_1_1_1[4]
SLICE_X97Y110.F3    net (fanout=1)       0.053 data_deintlv_30_1_1_1[4]/O
SLICE_X97Y110.X    Tilo                0.288 data_deintlv_30_1_1_1_0[4]
                                                   data_deintlv_30_1_1_1_0[4]
SLICE_X98Y112.G2    net (fanout=1)       0.304 data_deintlv_30_1_1_1_0[4]
SLICE_X98Y112.Y    Tilo                0.313 data_deintlv_c[4]
                                                   data_deintlv_30_1_1[4]
SLICE_X98Y112.F4    net (fanout=1)       0.075 data_deintlv_30_1_1[4]/O
SLICE_X98Y112.X    Tilo                0.288 data_deintlv_c[4]
                                                   data_deintlv_30_1[4]
SLICE_X98Y112.DX    net (fanout=1)       0.000 data_deintlv_30_1[4]/O
SLICE_X98Y112.CLK Tdxck                0.000 data_deintlv_c[4]
                                                   data_deintlv[4]
-------------------------------------------------  ---------------------------
Total                                     9.431ns (5.522ns logic, 3.909ns route)
                                                   (58.6% logic, 41.4% route)

--------------------------------------------------------------------------------
Slack:                -1.390ns (requirement - (data path - clock path skew + uncertainty))
  Source:             posi_q5[4] (FF)
  Destination:       data_deintlv[4] (FF)
  Requirement:       8.307ns
  Data Path Delay:    9.412ns (Levels of Logic = 13)
  Clock Path Skew:    -0.285ns (2.375 - 2.660)
  Source Clock:       clk_c rising at 0.000ns
  Destination Clock: clk_c rising at 8.307ns
  Clock Uncertainty: 0.000ns