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SAR ADC Application Note
ABSTRACT
Successive approximation register analog-to-digital converters (SAR ADCs) present a challenging load to the circuitry that drives the analog inputs. Specifications in data sheets may mislead the user into thinking that analog inputs, for example, are static, when in fact they create a highly dynamic load that requires specially designed buffer circuitry. This article looks at the architecture of modern SAR ADCs, specifically the application note, and examines the sampling and conversion processes in detail. This analysis highlights the considerations needed for designing input buffer circuitry to drive these ADCs with optimal results. |
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