something about Clock Gating[ZT]

triest

[size=100%]Clock tree consume more than 50 % of dynamic power. The components of this power are:
[size=100%]1) Power consumed by combinatorial logic whose values are changing on each clock edge[size=100%]
2) Power consumed by flip-flops and[size=100%]
3) The power consumed by the clock buffer tree in the design.
  [size=100%]It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

[size=100%]RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false.
   [size=100%]There are two types of clock gating styles available. They are:
[size=100%]1) Latch-based clock gating
2) Latch-free clock gating.
  

[size=130%]Latch free clock gating
  [size=100%]The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive  in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design.

                               
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[size=100%]Latch free clock gating

[size=130%]

[size=130%]Latch based clock gating
  [size=100%]The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.

                               
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[size=100%]    Latch based clock gating

  


[size=100%]Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.


   [size=130%]References
[size=100%][1] Frank Emnett and Mark Biegel, “Power Reduction Through RTL Clock Gating”, SNUG, San Jose, 2000
  [size=100%][2] PrimeTime User Guide

jttjtl

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qushaobo

不明所以，这种贴子