NO.14-Senior Product Engineer（Shanghai）

KT人才

Responsibility:
1.Attend whole Chip DFT architecture definition and DFT plan review.
2.Implement different schemes including SCAN, Boundary SCAN, MBIST and Analog micro test, trying to archive high coverage.
3.Generate different DFT patterns and verify them.
4.Maintain the DFT flow and support other teams in team of DFT problems.
5.Bring-up and debug the DFT patterns in ATE6.implementation, verification, especially DFT of complex communication and consumer ASICs

Requirement:
1.Bachelors with 3+ ASIC related experience or masters degree with 2 + related experience
2.Programming skills in VHDL, Verilog, C/C++ and any script language (such as unix shell, tcl, perl etc)
3.Working experience in DFT domain, basic knowledge on test concept, such as Boundary Scan, MEMORY BIST, DFT insertion flow, ATPG etc.
4.Familiar with ATE test flow, including pattern generation, simulation and conversion flow, test program debugging
5.Familiar with Design-Compiler, DFT-compiler, Tetramax or other EDA DFT tools6.Good communication, learning skills, fluent in spoken and written English

KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.

If you interested in the job, pls sent your cv to: gloria-hua@kthr.com, thanks!