顶级公司的AN：Characterizing Power-Supply Noise Rejection in PLL

yidao · 发表于 2010-6-22 01:13:19

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本帖最后由 yidao 于 2010-6-22 01:15 编辑

向牛公司的牛人学习！

Maxim公司的application note，关于PLL的电源抑制(PSRR)问题。关于PLL电源问题的好资料。
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实用指导
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Abstract

This application note discusses the effects of powersupply
noise interference on PLL-based clock
generators. It describes several measurement
techniques for evaluating the resulting DJ
(deterministic jitter). Relationships are derived
outlining how frequency-domain spur measurements
can be used to evaluate timing jitter behavior.
Laboratory bench-test results are used to compare
the approaches, and demonstrate how to reliably
assess the PSNR (power-supply noise rejection)
performance of a reference clock generator.

fdchou · 发表于 2010-6-23 15:02:13

Thank you very much!

yangbangbang · 发表于 2010-6-23 15:08:09

very good, thanks

sjxu007 · 发表于 2010-6-23 15:49:00

thanks

nchumitmatt · 发表于 2010-6-24 01:18:08

感謝分享~~~

EMC0101 · 发表于 2010-6-26 17:26:54

不错不错

s8553warrior · 发表于 2010-6-26 18:21:24

谢谢！！

zghway · 发表于 2010-7-6 15:28:27

赞AN

yxy7968 · 发表于 2010-7-7 08:22:55

thanks

fahongshui · 发表于 2010-7-7 08:33:50

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[资料] 顶级公司的AN：Characterizing Power-Supply Noise Rejection in PLL

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