急急急！！请教大虾怎么把这个Verilog 语言改写成VHDL语言?!程序的作用是什么啊？！

kscc0202121 · 发表于 2010-4-29 10:39:15

本帖最后由 kscc0202121 于 2010-4-29 10:42 编辑

module counter(clk,clr,out);
input clk;
input clr;
output reg out;
reg[11:0] cnt;
always @(posedge clk or negedge clr)
begin
if(!clr)
begin
out <= 1'b0;
cnt <= 12'b0;
end
else begin
cnt <= cnt + 1'b1;
if(cnt[11:0]==12'h9db)
begin
cnt <= 12'h0;
out <= 1'b0;
end
else if(cnt[11:0]==12'h9db)
begin
out <= 1'b1;
end
end
end
endmodule

csgood · 发表于 2010-4-29 10:39:16

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port(
clk,clr : in std_logic;
dout : out std_logic
);
end counter;

architecture arch of counter is
signal cnt : unsigned(11 downto 0);

begin

process(clk,clr)
begin
  if clr = '0' then
dout <= '0';
cnt  <= (others=>'0');
  elsif rising_edge(clk) then
cnt <= cnt + 1;
if cnt = x"9db" then
cnt  <= (others=>'0');
dout <= '0';
elsif cnt = x"456" then
dout <= '1';
end if;
  end if;
end process;

end arch;

NOTE: I changed the output port  'out'  in your codes to 'dout' since 'out' is a reserved word in VHDL, I can't assign any port with the name 'out'.

wycawyc · 发表于 2010-4-29 10:52:35

程序有错误。

falloutmx · 发表于 2010-4-29 13:21:10

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;

ENTITY counter IS
PORT
(
clk:in std_logic;
clr:in std_logic;
data_o

ut std_logic
);
END counter;

ARCHITECTURE arc OF counter IS

--ref signals
signal cnt:std_logic_vector(11 downto 0):=(others=>'0');
BEGIN

process(clr,clk)
begin
if clr='1' then
data_o<='0';
cnt<=(others=>'0');
elsif rising_edge(clk) then
if cnt/=X"9DB" then
cnt<=cnt+1;
data_o<='1';
else
cnt<=(others=>'0');
data_o<='0';
end if;
end if;
end process;

END arc;