我编写的一个8位拨码开关然后分频的程序.老有问题,,冰天雪地万分着急

pyy1980

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dvn IS
    PORT (clk,enn : IN STD_LOGIC;
             dfin: in std_logic_vector(7 downto 0);
             fout ut STD_LOGIC;
             fg ut STD_LOGIC
         );
END dvn;
ARCHITECTURE behav OF dvn IS
signal q1,q2,q3,m1,ck : STD_LOGIC;
signal dt: std_logic_vector(7 downto 0);
signal df,dg: std_logic_vector(7 downto 0);
begin
df<=dfin-"00000010";
dg<=dfin-1;
process(enn,clk,dfin,dg)
begin
if enn='0' then dt<="00000000";
elsif clk'event and clk='1' then
    if dt=dg then dt<="00000000";
       else  dt<=dt+1;
    end if;
end if;
if dt='0'&df(7 downto 1) then q1<='1';
else q1<='0';
end if;
end process;
ck<=q2 and (clk xor df(0));
process(q1,clk,m1)
begin
if m1='1' then q2<='0';
  elsif q1='1' then
      if clk'event and clk='1' then q2<='1';
      end if;
end if;
end process;
process(dt,clk,dg)
begin
if clk'event and clk='1' then
    if dt=dg then m1<='1';
    else m1<='0';   
end if;
end if;
end process;
process(ck,m1)
begin
if m1='1' then q3<='0';
elsif ck'event and ck='1' then q3<='1';
end if;
end process;
fout<=q3;
fg<=ck;
end behav;



程序如 上..老仿镇过不了,,哪个高人指点下....

pyy1980

ERROR:Cpld:853 - Insufficient number of product terms.  This design needs at least 297 but only 180 left after allocating other resources.
Device 9536XL44VQ was disqualified.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options.



在ISE软件中老是这样报错

MOSFET

器件容量不够？

pyy1980

哪个帮我看下应该在什么地方修改下??高人帮忙...

pyy1980

dddddddddddddd

pyy1980

DDDDDDDDDDDDDDDDDDD

falloutmx

It is probable that the fitter is attempting to collapse all logic into the fewest levels of logic for the highest speed performance. A drawback to this is that shared logic becomes duplicated and therefore consumes additional product term resources.

pyy1980

我编写的一个8位拨码开关然后分频的程序.老有问题,,冰天雪地万分着急哪个帮我修改下,,我时间太紧迫了

pyy1980

DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD

cksuperice

谢谢分享