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美国公司需要高级/staff级别验证人才，工作地点在上海。 Senior staff Read Channel Verification Engineer DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION: As a member of the Read Channel team, candidate must be willing to work as an extended member of the design team. Duties will include functional verification of Storage read channel mixed-signal IP. Candidate will be expected to contribute to design and development of System Verilog based verification environment and will be responsible for verification closure of block/chip/system level functions for mixed signal based IP. Experience with System Verilog and functional coverage methodologies are required. Must be willing to follow a disciplined verification methodology and to work closely with a multi-location, international design team. Excellent teamwork and communication skills are required. BSEE with 5-8+ years of design and/or verification experience required, MSEE preferred. Required knowledge and skills: - Expertise in System Verilog required - Good understanding of Digital Signal Processing - Good understanding of Analog and Digital Circuits - Very good analytical/debugging skill - Good verbal and written communication skills - Knowledge of Verilog-AMS, Perl - Knowledge of verification methodologies including functional coverage and constrained - Knowledge of VLSI design flows & DFT - Familiarity of high level programming language | 
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发表于 2010-4-20 13:43:02
