在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 2573|回复: 0

[招聘] 模拟设计, dc-dc, sigma delta, 收简历了 (美国公司成都办事处)

[复制链接]
发表于 2016-5-27 10:24:20 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
简历请发: adanshen@hotmail.com

As a member of Conexant Analog/Mixed-Signal group, you will work directly with a world-class team of IC designers in U.S to develop next generation Audio products. You will be responsible for the design, simulation and layout supervision of various analog blocks, and run chip level verification You will also participate in product definition and lab validation.
Requirements for this position are:

MS EE and 6+ years or PhD EE and 4+ years experience of CMOS analog/mixed-signal circuit design.

Solid knowledge in transistor-level analog CMOS design fundamentals, including operational amplifiers, noise analysis, continuous-time and discrete-time circuits
Good knowledge in high resolution sigma-delta A/D and D/A converters, Class-D PWM amplifiers, DC/DC converters is a plus
Experience with chip level simulation and analog-digital co-simulation experience is a strong plus

Strong knowledge in signal processing fundamentals
Experience with behavioral modeling tools such as Simulink, MATLAB, and VerilogA

Experience with Cadence IC design tools and analog simulation techniques

Hands-on experience with IC device testing and characterization

Candidate must be highly motivated and have strong written and verbal communication skills.

A team player, able to work effectively with peers or staff at all levels

Experience in doing actual layout work is a strong plus.
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-5 14:50 , Processed in 0.016944 second(s), 10 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表