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NVIDIA英伟达GPU部门急招ASIC Design高级、初级工程师!
一.投递方式 请将简历HR(Yvette)邮箱:yvettes@nvidia.com;
二.招聘岗位 1. ASIC Design Engineer—Computer Vision(GPU) Qualifications: Responsibilities: - Co-work with architect to define modulearchitecture/micro-architecture. - Building for NVIDIA next generation IPs - Involved in the whole ASIC flow. Minimum Requirement: - BS/MS in electrical/computer engineering andrelated. - 3+ years’ experience in ASIC design. Strongdesign/implementation skills in Verilog. Solid understanding in timing/poweroptimization skills of digital design. - Perl scripting skills is appreciated as aplus. - Video/Camera/ImagePostProcessing/ComputerVisionrelated experience is a big plus. - Fluent English (both written and spoken) andexcellent communication skills - Demonstrated ability to work independently aswell as in a multi-disciplinary group environment - Proactive & team work 2. Staff/Senior ASIC Design Engineer-Display(GPU) Job Description/Qualifications: The ASIC design engineer is expected to co-workwith architect to define architecture/micro-architecture, do RTL implementationand set up project milestones and drive design & verification progress andtrack project status. Minimum Requirement: - BS/MS in electrical/computer engineering andrelated. - At least 5+ year experience in ASIC design. - Strong design/implementation skills inVerilog. Solid understanding in timing/power optimization skills of digitaldesign. - Familiar with ASIC design flow such asmicro-arch spec definition and testplan documentation and code coverage andfunction coverage strategy. - Strong sense of design timing and area andclock skew issue. - Strong Perl/Csh scripting skills. - Fluent English (both written and spoken) andexcellent communication skills - Demonstrated ability to work independently aswell as in a multi-disciplinary group environment - Familiar with LCD/LVDS/DisplayPort/HDMI, vertical/horizontalscalar and color space is a big plus 3. ASIC Verification Engineer(GPU) Job Description/Qualifications: RESPONSIBILITIES: - RTL verification for various control logic andclocking logic in GPU/tegra chips. - Develop and maintain verification environmentat both full chip & unit level - Code/functional coverage analysis - Responsible for running both RTL & gatelevel simulation - Develop testing and regression methodologies - Develop/maintain/enhance environmenttools/scripts/makefiles MINIMUM REQUIREMENTS: - BSEE/MSEE/BSCS/MSCS with 3+/5+ years ofexperience in ASIC verification - Proficient in Verilog HDL - Familiar with logic simulators and debug tools(VCS, NCSIM, Verdi and etc.) - Working knowledge in C/C++, Makefile - Must have strong programming skills in one ormore scripting languages: TCL, Perl, Python - Knowledge/experience in one of the below areasis a big plus + UVM/VMM experience + ARM based SoC verification experience PCIE/USBverification experience + CPU verification experience Clockingverification experience |