|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
前面生成波特率部分是按照例程写的。后面的状态机移位输出程序是自己写的。实现的功能是要按下txd_start这个键后要输出个AA来。但是接收到的数确是FF,郁闷坏了。我把程序贴出来给大家帮忙看下吧,多谢了。中间有一段程序时txd_start这个按键的消抖程序。另外,第二个always块的敏感表我试过改成CS和BaudTick也不好使
-
- module uart_send(clk,nrst,txd_start,txd);
- input clk,nrst,txd_start;
- output reg txd;
- parameter Baud = 9600;
- parameter Clock = 50_000_000;
- parameter BaudAccWidth = 16;
- wire [BaudAccWidth:0]BaudAccInc = (Baud<<(BaudAccWidth-4)+(Clock>>5))/(Clock>>4);
- reg [BaudAccWidth:0]BaudAcc;
-
- //产生波特率时钟
- always @(posedge clk) BaudAcc<=BaudAcc[BaudAccWidth-1:0]+BaudAccInc;
- wire BaudTick=BaudAcc[BaudAccWidth];
- reg dout1,dout2,dout3,buff;
- reg div_clk; //分频时钟
- reg[16:0]count; //时钟分频计数器
-
- //时钟分频部分
- always @(posedge clk)
- begin
- if (count < 17'd120000)
- begin
- count <= count + 1'b1;
- div_clk <= 1'b0;
- end
- else
- begin
- count <= 17'd0;
- div_clk <= 1'b1;
- end
- end
-
- //按键消抖部分
- always @(posedge clk)
- begin
- if(div_clk)
- begin
- dout1 <= txd_start;
- dout2 <= dout1;
- dout3 <= dout2;
- end
- end
-
- //按键边沿检测部分
- always @(posedge clk)
- begin
- buff <= dout1 | dout2 | dout3;
- end
-
- wire key_edge_out;
- assign key_edge_out = ~(dout1 | dout2 | dout3) & buff;
-
-
- //状态机发送数据
- reg [3:0]CS,NS;
- parameter IDLE=4'b0000,
- READY=4'b0001,
- START=4'b0010,
- BIT0=4'b0011,
- BIT1=4'b0100,
- BIT2=4'b0101,
- BIT3=4'b0110,
- BIT4=4'b0111,
- BIT5=4'b1000,
- BIT6=4'b1001,
- BIT7=4'b1010,
- STOP=4'b1011,
- STOP2=4'b1100;
-
- always@(posedge clk or negedge nrst)
- begin
- if(!nrst)
- CS<=IDLE;
- else
- CS<=NS;
- end
-
- always@(*)
- begin
- NS=4'bxxxx;
- case(CS)
- IDLE: begin if(key_edge_out) NS=READY; else NS=IDLE; end
- READY: begin if(BaudTick) NS=START; else NS=READY; end
- START: begin if(BaudTick) NS=BIT0; else NS=START; end
- BIT0: begin if(BaudTick) NS=BIT1; else NS=BIT0; end
- BIT1: begin if(BaudTick) NS=BIT2; else NS=BIT1; end
- BIT2: begin if(BaudTick) NS=BIT3; else NS=BIT2; end
- BIT3: begin if(BaudTick) NS=BIT4; else NS=BIT3; end
- BIT4: begin if(BaudTick) NS=BIT5; else NS=BIT4; end
- BIT5: begin if(BaudTick) NS=BIT6; else NS=BIT5; end
- BIT6: begin if(BaudTick) NS=BIT7; else NS=BIT6; end
- BIT7: begin if(BaudTick) NS=STOP; else NS=BIT7; end
- STOP: begin if(BaudTick) NS=STOP2; else NS=STOP; end
- STOP2: NS=IDLE;
- default: NS=IDLE;
- endcase
- end
-
- always @(posedge clk or negedge nrst)
- begin
- if(!nrst)
- txd<=1;
- else
- begin
- case(NS)
- IDLE: txd<=1;
- READY: txd<=1;
- START: txd<=0;
- BIT0: txd<=0;
- BIT1: txd<=1;
- BIT2: txd<=0;
- BIT3: txd<=1;
- BIT4: txd<=0;
- BIT5: txd<=1;
- BIT6: txd<=0;
- BIT7: txd<=1;
- STOP: txd<=1;
- STOP2: txd<=1;
- default: txd<=1;
- endcase
- end
-
- end
- endmodule
-
复制代码 |
|