同一个时钟的如何设置false_path

defflin

有一个时钟，和它的反相时钟，不存在上升沿采下降沿的情况，如何设置false_path ?

psd0208

不明白你是什么意思
是要将该时钟和他的反相时钟设为false path么？

defflin

2# psd0208

不是，这样问题早解决了。
问题是timing 报告里面，显示的是同一个时钟的上升沿去采它下降沿发射的数据，真令人费解。

ineedpower

不明白你在说什么...

jiku

最好不要乱设false path. 还是看清电路先。

abnerliu

it means:
you created 2 clocks with same clock source.
For ex;
1. create_clock .... clk_source
    cretate_generated_clock ..... -source clk_source             ... clk_a
    create_generated_clock  ..... -source clk_source -revert ... clk_b
your violation happens between clk_a and clk_b

please divided these 2 clocks, then set false path, then this question solved.

for ex:
create_clock .... clk_a ( dont use -source option )
create_clock .... clk_b ( dont use -source option )
set_false path -from [get_clocks clk_a] -to [get_clocks clk_b]

abnerliu

Or, you just define 1 clock, but sta tools automatically finds you have
2 clock types ( 1 is positive, the other is negative )

The only thing you need to do is to separate and define them, then set
false path.

defflin

7# abnerliu
谢谢