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Some papers about ESD design using SCR.
1. Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25 um CMOS process
2. SCR Device With Double-Triggered Technique for On-Chip ESD Protection in Sub-Quarter-Micron Silicided CMOS Processes
3. Latchup-free esd protection design with complementary substrate-triggered scr devices
4. Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology
5. Overview of On-Chip Electrostatic Discharge Protection Design With SCR-Based Devices in CMOS Integrated Circuits |
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发表于 2010-1-10 00:00:34
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