design for test standard

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TABLE OF CONTENTS
ACRONYMS
GLOSSARY
1. BASIC TEST CONCEPTS
1.1 Fault modeling and ss@ faults ............................................................ 1.1
1.2 Controllability, observability and testability ..................................... 1.2
1.3 Test vector generation for combinational circuits.............................. 1.4
1.4 Testability and test generation in sequential circuits ....................... 1.7
1.5 Testability improvement via ad hoc solutions.................................. 1.11
1.6 Structured approaches to design for testability ............................... 1.12
1.7 Hands-on............................................................................................ 1.20
2. THE BOUNDARY SCAN TEST (BST) TECHNOLOGY
2.1 The development of BST and its application domain ........................ 2.1
2.2 The BS architecture and test access port (TAP) ................................ 2.2
2.2.1 The basic boundary scan cell....................................................................2.5
2.2.2 The test data registers..............................................................................2.6
2.2.3 The instruction register............................................................................2.7
2.2.4 The TAP controller ...................................................................................2.8
2.3 Implementation of an 1149.1 BST architecture on a MACH
programmable logic device ................................................................ 2.10
2.4 Hands-on............................................................................................ 2.19
2.4.1 BST infrastructure validation................................................................2.19
2.4.2 BST infrastructure expansion for fault tolerance validation ................ 2.20
2.4.3 BST infrastructure expansion for real-time breakpoint detection........ 2.21
3. TEST PROTOCOL FOR BST BOARDS
3.1 Fault detection in the BS infrastructure ............................................ 3.1
3.2 Open fault detection in full-BST interconnections............................. 3.3
3.3 Short-circuit fault detection among full-BST interconnections......... 3.4
3.4 Full-BST interconnect testing in boards with multiple BS chains ... 3.6
3.5 Fault detection in non-BS clusters ..................................................... 3.7
3.6 Testing non-BS clusters in boards with multiple BS chains ............. 3.8
3.7 Faulty components detection .............................................................. 3.8
4. A BS TEST CONTROLLER MODEL
4.1 Basic test operations ........................................................................... 4.1
4.1.1 Basic test operations to control the BS infrastructure ............................4.1
4.1.2 Basic test operations to synchronise the BS infrastructure with
external test resources..............................................................................4.2
4.1.3 Basic test operations to control internal resources and test program
flow............................................................................................................4.3
4.2 The test instruction set ....................................................................... 4.4
4.2.1 Control of the BS infrastructure ......................................................... 4.4
4.2.2 Synchronisation with external test resources .................................... 4.6
4.2.3 Control of internal resources and test program flow ......................... 4.7
4.3 Test program generation..................................................................... 4.7
5. A CASE STUDY OF TEST PROGRAM GENERATION
5.1 The demonstration board .................................................................... 5.1
5.2 The information required for test program generation ..................... 5.2
5.2.1 Integrity check of the BS infrastructure..................................................5.3
5.2.2 Full-BS interconnects test ........................................................................5.3
5.2.3 Non-BS clusters test .................................................................................5.6
5.2.4 Components test .......................................................................................5.9
5.3 The test vectors.................................................................................. 5.10
5.3.1 Test vectors for short-circuit detection in full-BS interconnects........... 5.11
5.3.2 The complete set of serialised test vectors, expected responses and
mask data................................................................................................5.11
5.4 The test program ............................................................................... 5.21
6. A WINDOWS BS TEST CONTROLLER APPLICATION
6.1 Test set up............................................................................................ 6.1
6.2 The test controller application ............................................................ 6.2
6.2.1 Test program control bar..........................................................................6.3
6.2.2 Status information....................................................................................6.4
6.2.3 Pop-down menus.......................................................................................6.4
6.2.4 Editing area ..............................................................................................6.5
6.3 Exhaustive testing of non-BS clusters................................................ 6.6
6.4 Non-BS cluster testing with PRPG and SA...................................... 6.10
6.4.1 Determining the correct signature......................................................... 6.11
6.4.2 The required number of PRPG test vectors ........................................... 6.13
6.5 Hands-on............................................................................................ 6.15
6.5.1 Fault detection through deterministic test vectors ...............................6.15
6.5.2 Fault detection through pseudo-random test vectors ............................6.15
7. AN INTRODUCTION TO BUILT-IN SELF-TEST (BIST)
7.1 BIST architecture at IC level .............................................................. 7.1
7.1.1 Test vector generation and application....................................................7.3
7.1.2 Response capture and evaluation.............................................................7.4
7.1.3 BIST controller .........................................................................................7.4
7.2 BIST of combinational circuits............................................................ 7.5
7.2.1 Pseudo-random test vector generation.....................................................7.5
7.2.2 Response compaction by signature analysis ............................................7.8
7.3 BIST of sequential circuits ..................................................................... 7.10
7.4 BIST of macro-cells................................................................................. 7.10
7.4.1 Low / medium complexity macro-cells.................................................... 7.11
7.4.2 BIST of megacells: the IEEE P1500 proposed standard........................ 7.11
7.5 Interface between BIST and the BST infrastructure....................... 7.12
7.5.1 Architecture of a BST component with BIST......................................... 7.12
7.5.2 The RUNBIST instruction revisited ...................................................... 7.13
7.5.3 Hierarchical BIST................................................................................... 7.14
7.6 Design for testability and BIST in the Pentium Pro processor ....... 7.15
7.7 Hands-on............................................................................................ 7.18
8. INTRODUCTION TO MIXED-SIGNAL TESTING USING THE IEEE
1149.4 STANDARD
8.1 Scope of the IEEE 1149.4 standard .................................................... 8.1
8.2 1149.4 Overview .................................................................................. 8.2
8.2.1 The basic 1149.4 architecture...................................................................8.2
8.2.2 1149.4 test register structure ...................................................................8.4
8.2.3 1149.4 instructions ...................................................................................8.4
8.3 1149.4: The main blocks ...................................................................... 8.5
8.3.1 The Test Bus Interface Circuit (TBIC).....................................................8.5
8.3.2 The Analog Boundary Modules (ABM) ....................................................8.8
8.4 Interconnect testing with 1149.4 ...................................................... 8.10
8.5 Impedance measurements with 1149.4 ............................................ 8.10
8.5.1 Impedance between pin and ground ...................................................... 8.11
8.5.2 Impedance between two pins.................................................................. 8.12
8.6 1149.4: Further information ............................................................. 8.13
8.7 Hands-on............................................................................................ 8.15
8.7.1 Control of the 1149.4 test infrastructure at IC level .............................8.16
8.7.2 Design of an 1149.4 test infrastructure ................................................. 8.16
8.7.3 Implications of 1149.4 at the test controller level.................................. 8.16
9. REFERENCES
9.1 Books .................................................................................................... 9.1
9.2 Standards, magazine articles and conference papers ........................ 9.4

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求助《Testing Static Random Access Memories: Defects, Fault Models and Test Patterns》
急需。

yizhibi01022

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pedro888

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