下面两个verilog代码（非阻塞和阻塞）转换成VHDL应该是什么样的呀？请高手指点

freebetter

1）取上沿逻辑，非阻塞语句
always @ ( posedge clk_122m88 or posedge reset )
begin
    if( reset == 1'b1 )
    begin        
       frame_10ms_1reg <= 1'b0;
       frame_10ms_2reg <= 1'b0;
       frame_10ms_pose <= 1'b0;
    end
    else   
    begin                    
       frame_10ms_1reg <= frame_10ms;
       frame_10ms_2reg <= frame_10ms_1reg;
       frame_10ms_pose <= ~frame_10ms_2reg & frame_10ms_1reg;
    end
end
2）二进制格雷码转换，阻塞语句
always @ ( posedge clk_122m88 or posedge reset)
begin
    if ( reset == 1'b1)
        wr_addr_tx_g = 5'b0;
    else
    begin
        wr_addr_tx_g[4] = wr_addr_tx[4];
        wr_addr_tx_g[3] = wr_addr_tx[4] ^ wr_addr_tx[3];
        wr_addr_tx_g[2] = wr_addr_tx[3] ^ wr_addr_tx[2];
        wr_addr_tx_g[1] = wr_addr_tx[2] ^ wr_addr_tx[1];
        wr_addr_tx_g[0] = wr_addr_tx[1] ^ wr_addr_tx[0];
    end
end