LDO current limit

alfredchn · 发表于 2009-10-14 22:00:28

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摘要：本文提出的过流保护电路利用运算放大器虚短虚断的原理大大提高了对输出电流的采
样精度，从而提高了电路的可靠性；并通过增加的折回电路，有效降低了LDO（Low
Drop-Out）系统的过流关断功耗。本电路基于TSMC 0.6μ m CMOS 工艺设计，进行了应用
于LDO 的Spectra 仿真，结果表明该过流保护电路可靠性高、过流关断功耗低。

一种新型过流保护电路的设计研究.pdf (111.01 KB, 下载次数: 1561 )

Abstract: This paper introduces the design of a l.8 V low dropout voltage regulator (LDO) and a foldback current
limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in
a 0.18 m CMOS technology. The measured result reveals that the LDO0s power supply rejection (PSR) is about
􀀀58 dB and –54 dB at 20 Hz and 1 kHz respectively, the response time is 4 s and the quiescent current is 20 A.
The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a
maximum load current of 240 mA.

A 1.8 V LDO voltage regulator with foldback current limit and thermal protection.pdf (576.08 KB, 下载次数: 752 )