FPGA Implementation of FIR Filters Using Add and Shift Method

kevinwjs

a method for implementing high speed
Finite Impulse Response (FIR) filters using just registered adders
and hardwired shifts. We extensively use a modified common
subexpression elimination algorithm to reduce the number of
adders. We target our optimizations to Xilinx Virtex II devices
where we compare our implementations with those produced by
Xilinx CoregenTM using Distributed Arithmetic. We observe up
to 50% reduction in the number of slices and up to 75%
reduction in the number of LUTs for fully parallel
implementations. We also observed up to 50% reduction in the
total dynamic power consumption of the filters. Our designs
perform significantly faster than the MAC filters, which use
embedded multipliers.

manonroad

thanks

manonroad

thanks

primemm

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xsteven2

have a look
thanks

xsteven2

thanks a lot

ericchen228

Thanks for sharing!

vikingg

谢谢分享

lqpcwl1986

THANKS

systemsim004

回复 1# kevinwjs


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