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发表于 2009-8-17 00:14:50
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in verilog 95, in fact, there's no such things about signed or unsigned numbers. It's just some bits.
e.g. reg[3:0] num;
initial begin
num = 4'd15; // then num is 0xf.
end
And 0xf is simply 0x1's 2's complement...
in other words, say, would'd like to do something like:
reg[3:0] a;
reg[3:0] b;
reg[7:0] c;
initial begin
a = -1;
b = -1;
c = a * b;
end
c would be 0xe1, not 1...
So you'd have to take care of your sign instead.
In v2k, it's better, there's a reserved word called signed.
reg[3:0] signed a;
reg[3:0] signed b;
reg[7:0] signed c;
now c = 1. |
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