unique chips and system

西湖水

Preface ........................................................................................................ vii
Editors ..........................................................................................................xi
Contributors ............................................................................................. xiii
1 Architecture and Implementation of the TRIPS Processor ..........1
Stephen W. Keckler, Doug Burger, Karthikeyan Sankaralingam, Ramadass
Nagarajan, Robert McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S.
Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim,
Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif,
and Premkishore Shivakumar
2 High-Performance Data Security in an x86 Processor ................ 41
G. Glenn Henry, Terry Parks, and Tom Crispin
3 arm Cortex-A8: A High-Performance Processor
for Low-Power Applications ........................................................... 79
David Williamson
4 A Rotated Array Clustered Extended Hypercube
Processor: The RACE-HTM Processor .......................................... 107
Gerald G. Pechanek, Mihailo Stojancic, Frank Barry,
and Nikos Pitsianis
5 A High-Throughput Self-Timed FPGA Core Architecture ....... 125
Brian C. Gaide and Lizy Kurian John
6 The Continuation-Based Multithreading Processor: Fuce........ 177
Masaaki Izumi, Satoshi Amamiya, Takanori Matsuzaki,
and Makoto Amamiya
7 AStudy of a Processor with Dual Thread Execution Modes .... 197
Rania Mameesh and Manoj Franklin
vi Contents
8 Measurement-Based Power Phase Analysis ............................... 217
W. Lloyd Bircher and Lizy Kurian John
9 Visualization by Subdivision: Two Applications
for Future Graphics Platforms ...................................................... 239
Chand T. John
10 A Performance Analysis of Two-Level Heterogeneous
Processing Systems on Wavefront Algorithms .......................... 259
Darren J. Kerbyson and Adolfy Hoisie
11 Microarchitectural Characteristics and Implications
of Alignment of Multiple Bioinformatics Sequences ................ 281
Tao Li
12 Towards System-Level Fault-Tolerance Using Formal
Methods and SoC Methodologies ................................................ 299
Kristina Lundqvist
13 Forward Error Correction for On-Chip Interconnection
Networks .......................................................................................... 325
Praveen Bhojwani, Rohit Singhal, Gwan Choi, and Rabi Mahapatra
14 Alleviating Thermal Constraints while Maintaining
Performance via Silicon-Based On-Chip
Optical Interconnects ..................................................................... 339
Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen,
Hui Chen, Eby G. Friedman, Philippe M. Fauchet, and David H. Albonesi
Index .......................................................................................................... 357