乘法器问题（vhdl)

hefeng84928

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY multplier2 is
generic(M: integer:=8 );
  port(  dataA: IN STD_LOGIC_VECTOR(M-1 DOWNTO 0);
         dataB: IN STD_LOGIC_VECTOR(M-1 DOWNTO 0);
         result: out std_logic_vector(M+M-1 DOWNTO 0));
END multplier2 ;
ARCHITECTURE BEH OF multplier2 is
begin
inset_mult: process(dataA,dataB)
variable dataA_temp,dataB_temp,temp: std_logic_vector(M-1 DOWNTO 0);
variable count: integer:= 0;
begin
    dataA_temp := dataA;
    dataB_temp := dataB;
    temp:="00000000";
    while count<M-1 LOOP
          if ( dataA(count)='1') then
            temp:= temp+ dataB_temp;
          end if;
     dataA_temp := temp(0) & dataA_temp(M-1 DOWNTO 1);
     temp := '0' & temp(M-1 TO 1);
     count := count + 1;
    end loop;
    result<=temp & dataA_temp;
END process inset_mult;
end architecture BEH;


编译后报
Error (10327): VHDL error at multplier2.vhd(21): can't determine definition of operator ""+"" -- found 0 possible definitions
错误
是什么原因啊
temp:= temp+ dataB_temp这句没有错啊

liulanghan

“ if ( dataA(count)='1') then”
是不是dataA(count)='1'的问题？

manfeihappy

看看 接着评论

manfeihappy

先看看看看

guot

将USE IEEE.STD_LOGIC_ARITH.ALL;换成unsigned这个包

davidwx54

将USE IEEE.STD_LOGIC_ARITH.ALL;换成unsigned这个包
楼上说得对

zbzxj0118

将USE IEEE.STD_LOGIC_ARITH.ALL;换成unsigned这个包
楼上说得对