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我刚解决了一个问题，就是将encounter里的gds能够“完全”导入virtuoso能够显示.先给大家分享一下，希望能够给有相同难题的同仁带来一些帮助：
开始的时候encounter导GDS出来的时候有个streamout.map这个文件我以为是输出文件就没有管它，后来发现导入virtuoso里的metal层和via这些都不对。经过请教才发现encounter导GDS时的streamout.map文件是输入文件，而不是输出文件，所以我就按照virtuoso里的tf文件的定义改了层位置，再从encounter里导出GDS，这样在virtuoso里就可以发现metal层和via都是正确的。
我本以为这样就可以了，但是我在做DRC的时候确报错了。
错误信息如下：
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two NW regions with the same potential is 0.60um
Merge if space is less than 0.6um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M2 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M2 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M3 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M3 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum area of a M3 region is 0.20um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M4 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum width of an M5 region is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two M5 regions is 0.28um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V1 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V2 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V3 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two V4 is 0.26um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum/maximum size of a VT is 0.36um
Rule File Pathname: /home/cwg/cds/_SmicDR4P6P_cal018_mixlog_sali_p1mt6_1833.drc_
Minimum space between two VT is 0.35um
从错误信息来看，encounter在自动布线时via to via,metal to metal 和via to metal的间距都没有考虑，所以在DRC的时候就报了很多这样的错误。
请问是不是LEF文件（Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R）和DRC文件（Date: 2007/08/06）的版本不匹配？还是我在encounter里导出GDS前修改的streamout.map有问题呢？还是有别的原因呢？
下面是LEF文件的版本信息(1)，DRC的版本信息(2)，tf文件在层次上的定义(3)和我在encounter streamout时修改后的streamout.map文件(4)：
（1）：LEF版本信息
#******
# TECH LIB NAME: smic18
# TECH FILE NAME: techfile.cds
#
# RC values have been extracted from SMIC's Interconnect Capacitance
# Table, Rev 2.0, Date 02-08-2003 and Document TD-L018-BL-2001 Rev 2R
#
# Resistance and Capacitance Values
# ---------------------------------
# The LEF technology files included in this directory contain
# resistance and capacitance (RC) values for the purpose of timing
# driven place & route. Please note that the RC values contained in
# this tech file were created using the worst case interconnect models
# from the foundry and assume a full metal route at every grid location
# on every metal layer, so the values are intentionally very
# conservative. It is assumed that this technology file will be used
# only as a starting point for creating initial timing driven place &
# route runs during the development of your own more accurate RC
# values, tailored to your specific place & route environment. AS A
# RESULT, TIMING NUMBERS DERIVED FROM THESE RC VALUES MAY BE
# SIGNIFICANTLY SLOWER THAN REALITY.
#
# The RC values used in the LEF technology file are to be used only
# for timing driven place & route. Due to accuracy limitations,
# please do not attempt to use this file for chip-level RC extraction
# in conjunction with your sign-off timing simulations. For chip-level
# extraction, please use a dedicated extraction tool such as HyperExtract,
# starRC or Simplex, etc.
#
# $Id: smic18_6lm.lef,v 1.4 2003-03-10 18:30:04-08 wching Exp $
#
#******
VERSION 5.2 ;
（2）：DRC的版本信息：
//$Author: Karen Kang
//$Revision: 1.1
//$Date: 2007/08/06 01:03:59 $
//=================================================================================
//| |
//| 0.18um 1P6M Calibre DRC rule file for |
//| |
//| SMIC: 0.18um LOGIC 1P6M Salicide 1.8V/3.3V Design Rule |
//| Doc. No.: TD-LO18-DR-2001 Rev.: 4 T |
//| |
//| SMIC: 0.18um Mixed-Signal 1P6M Salicide 1.8V/3.3V Design Rule |
//| Doc. No.: TD-MM18-DR-2001 Rev.: 6 P |
//| |
//| SMIC DSD Technologies |
(3):tf文件在层次上的定义
( M1 61 M1 )
( M2 62 M2 )
( M3 63 M3 )
( M4 64 M4 )
( M5 65 M5 )
( M6 66 M6 )
( V1 70 V1 )
( V2 71 V2 )
( V3 72 V3 )
( V4 73 V4 )
( V5 74 V5 )
( OPCBA 100 OPCBA )
( OPCBP 101 OPCBP )
( OPCBM 102 OPCBM )
( M1TXT 141 M1TXT )
( M2TXT 142 M2TXT )
( M3TXT 143 M3TXT )
( M4TXT 144 M4TXT )
( M5TXT 145 M5TXT )
( M6TXT 146 M6TXT )
(4)：在encounter streamout时修改后的streamout.map文件
METAL1 NET 61 0
METAL1 SPNET 61 0
METAL1 PIN 61 0
METAL1 LEFPIN 61 0
METAL1 FILL 61 0
METAL1 VIA 61 0
METAL1 VIAFILL 61 0
METAL1 LEFOBS 61 0
NAME METAL1/NET 141 0
NAME METAL1/SPNET 141 0
NAME METAL1/PIN 141 0
NAME METAL1/LEFPIN 141 0
VIA12 FILL 70 0
VIA12 VIA 70 0
VIA12 VIAFILL 70 0
METAL2 NET 62 0
METAL2 SPNET 62 0
METAL2 PIN 62 0
METAL2 LEFPIN 62 0
METAL2 FILL 62 0
METAL2 VIA 62 0
METAL2 VIAFILL 62 0
METAL2 LEFOBS 62 0
NAME METAL2/NET 142 0
NAME METAL2/SPNET 142 0
NAME METAL2/PIN 142 0
NAME METAL2/LEFPIN 142 0
VIA23 FILL 71 0
VIA23 VIA 71 0
VIA23 VIAFILL 71 0
METAL3 NET 63 0
METAL3 SPNET 63 0
METAL3 PIN 63 0
METAL3 LEFPIN 63 0
METAL3 FILL 63 0
METAL3 VIA 63 0
METAL3 VIAFILL 63 0
METAL3 LEFOBS 63 0
NAME METAL3/NET 143 0
NAME METAL3/SPNET 143 0
NAME METAL3/PIN 143 0
NAME METAL3/LEFPIN 143 0
VIA34 FILL 72 0
VIA34 VIA 72 0
VIA34 VIAFILL 72 0
METAL4 NET 64 0
METAL4 SPNET 64 0
METAL4 PIN 64 0
METAL4 LEFPIN 64 0
METAL4 FILL 64 0
METAL4 VIA 64 0
METAL4 VIAFILL 64 0
METAL4 LEFOBS 64 0
NAME METAL4/NET 144 0
NAME METAL4/SPNET 144 0
NAME METAL4/PIN 144 0
NAME METAL4/LEFPIN 144 0
VIA45 FILL 73 0
VIA45 VIA 73 0
VIA45 VIAFILL 73 0
METAL5 NET 65 0
METAL5 SPNET 65 0
METAL5 PIN 65 0
METAL5 LEFPIN 65 0
METAL5 FILL 65 0
METAL5 VIA 65 0
METAL5 VIAFILL 65 0
METAL5 LEFOBS 65 0
NAME METAL5/NET 145 0
NAME METAL5/SPNET 145 0
NAME METAL5/PIN 145 0
NAME METAL5/LEFPIN 145 0
VIA56 FILL 74 0
VIA56 VIA 74 0
VIA56 VIAFILL 74 0
METAL6 NET 66 0
METAL6 SPNET 66 0
METAL6 PIN 66 0
METAL6 LEFPIN 66 0
METAL6 FILL 66 0
METAL6 VIA 66 0
METAL6 VIAFILL 66 0
METAL6 LEFOBS 66 0
NAME METAL6/NET 146 0
NAME METAL6/SPNET 146 0
NAME METAL6/PIN 146 0
NAME METAL6/LEFPIN 146 0
NAME COMP 101 0
COMP ALL 102 0
DIEAREA ALL 112 0
大家看看究竟是什么原因呢？
是map文件修改后又问题呢？还是encounter里用的lef文件和virtuoso里用的tf文件版本不匹配（或者说是lef文件rule不全）呢？ |
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发表于 2009-3-13 22:52:38
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