cpld太热了！求救问答

haichao

问题：
cpld上电后，半分钟内就热起来了，相当热！有点灼手。
测了电源的引脚，都是5v。
没用上的I/O都悬空，电压基本上为0V；而有两个悬空脚上是5V的；
在maxii中直接用默认的方式编译，下载代码。
在全局逻辑综合选项中，选择了引脚自动开漏，
时钟、清零、复位和输出使能都选上了。
不知道问题出现在哪里，请各位帮忙看看，提点建议。
答：
a few approches to avoid this or similar:
1) Unused pins should not float. Floating input receivers can reside at a totally arbitrary level and may induce input stages to draw as much as 10 mA per pin. This factor is easily remedied by driving the pins to known
CMOS levels. One easy way to do this is to simply invoke the User Programmable Ground Option (UPG). Care must be taken that these pins are indeed unused
and not reserved for future functionality. They will be driven to ground and if wished, may be externally attached to the PCB ground to provide additional chip
grounding.
2) Use global resources where possible. Overusing clocks, sets, resets and OEs can add up in the power budget.
3) Restricting the voltage swing of the output stage will lower the power consumed. It may impact other chips that expect a larger voltage range, but can dramatically lower power consumed in the CPLD.
4) Because most CPLD users seek raw speed, the defaults with macrocells
configured for high speed. Which also takes the most current. By carefully selecting only those macrocells that need be in high speed mode.

5) Minimize Function Blocks used. If a single macrocell occupies a Function Block, the Function Block will be turned “on”. When this occurs, all unused macrocells in that FB will be powered up to at least the low power Bitline high condition.

hnzh201

版主能给解释的再清楚点吗？有中文说明的比较好的解决办法吗？谢谢版主了

szgr

没用的PIN应该接相应的电平，不应该悬空。

55555

目前解决了吗？如何解决的？为什么？

mxqian

好东西。顶。

richardz

very good!

zly586

哪个型号,把资料再好好看看.