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Power Distribution Networks with On-Chip Decoupling Capacitors

Product Details

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Hardcover: 515 pages

·
Publisher: Springer; 1 edition (November 15, 2007)

·
Language: English

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ISBN-10: 0387716009

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ISBN-13: 978-0387716008

Description:
Power Distribution Networks with On-Chip Decoupling Capacitors is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding tens of watts and the power supply below a volt. The book provides insight and intuition into the behavior and design of integrated circuit-based power distribution systems.
The book has three primary objectives. The first is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for effciently placing on-chip decoupling capacitors in nanoscale integrated circuits.
Power Distribution Networks with On-Chip Decoupling Capacitors is a reference for professional engineers in the fields of circuits and systems and computer-aided design.

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目录：


1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Evolution of integrated circuit technology . . . . . . . . . . 3
1.2 Evolution of design objectives. . . . . . . . . . . . . . . . . . . . . 7
1.3 The problem of power distribution . . . . . . . . . . . . . . . . 10
1.4 Deleterious effects of power distribution noise . . . . . . . 17
1.4.1 Signal delay uncertainty . . . . . . . . . . . . . . . . . . . . 17
1.4.2 On-chip clock jitter . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.3 Noise margin degradation. . . . . . . . . . . . . . . . . . . 20
1.4.4 Degradation of gate oxide reliability . . . . . . . . . . 20
1.5 Book outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Inductive Properties of Electric Circuits . . . . . . . . . . 27
2.1 Definitions of inductance . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.1 Field energy definition . . . . . . . . . . . . . . . . . . . . . 28
2.1.2 Magnetic flux definition . . . . . . . . . . . . . . . . . . . . 30
2.1.3 Partial inductance . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.1.4 Net inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.2 Variation of inductance with frequency . . . . . . . . . . . . . 43
2.2.1 Uniform current density approximation . . . . . . . 44
2.2.2 Inductance variation mechanisms . . . . . . . . . . . . 45
2.2.3 Simple circuit model . . . . . . . . . . . . . . . . . . . . . . . 49
2.3 Inductive behavior of circuits . . . . . . . . . . . . . . . . . . . . . 52
2.4 Inductive properties of on-chip interconnect . . . . . . . . 54
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3 Properties of On-Chip Inductive Current Loops . . . 59
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2 Dependence of inductance on line length . . . . . . . . . . . 60
3.3 Inductive coupling between two parallel loop segments 67
3.4 Application to circuit analysis . . . . . . . . . . . . . . . . . . . . 68
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4 Electromigration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.1 Physical mechanism of electromigration . . . . . . . . . . . . 72
4.2 Electromigration-induced mechanical stress . . . . . . . . . 75
4.3 Steady state limit of electromigration damage . . . . . . . 76
4.4 Dependence of electromigration lifetime on the line dimensions
. . . . . . . . . 78
4.5 Statistical distribution of electromigration lifetime . . . 81
4.6 Electromigration lifetime under AC current . . . . . . . . . 82
4.7 Electromigration in novel interconnect technologies . . 83
4.8 Designing for electromigration reliability . . . . . . . . . . . 85
4.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5 High Performance Power Distribution Systems. . . . 87
5.1 Physical structure of a power distribution system . . . . 88
5.2 Circuit model of a power distribution system . . . . . . . 89
5.3 Output impedance of a power distribution system . . . 92
5.4 A power distribution system with a decoupling
capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5.4.1 Impedance characteristics . . . . . . . . . . . . . . . . . . . 95
5.4.2 Limitations of a single-tier decoupling scheme . 99
5.5 Hierarchical placement of decoupling capacitance . . . . 101
5.6 Resonance in power distribution networks . . . . . . . . . . 108
5.7 Full impedance compensation . . . . . . . . . . . . . . . . . . . . . 114
5.8 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.9 Design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5.9.1 Inductance of the decoupling capacitors . . . . . . 119
5.9.2 Interconnect inductance . . . . . . . . . . . . . . . . . . . . 120
5.10 Limitations of the one-dimensional circuit model . . . . 121
5.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6 Decoupling Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.1 Introduction to decoupling capacitance. . . . . . . . . . . . . 126
6.1.1 Historical retrospective . . . . . . . . . . . . . . . . . . . . . 126
6.1.2 Decoupling capacitor as a reservoir of charge . . 127
6.1.3 Practical model of a decoupling capacitor . . . . . 129

6.2 Impedance of power distribution system with
decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.2.1 Target impedance of a power distribution system . .. . . . . . . . . . . . . . . . . . . 133
6.2.2 Antiresonance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.2.3 Hydraulic analogy of hierarchical placement of
decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . 140
6.3 Intrinsic vs intentional on-chip decoupling capacitance 145
6.3.1 Intrinsic decoupling capacitance . . . . . . . . . . . . . 146
6.3.2 Intentional decoupling capacitance . . . . . . . . . . . 150
6.4 Types of on-chip decoupling capacitors . . . . . . . . . . . . . 152
6.4.1 Polysilicon-insulator-polysilicon (PIP) capacitors . . .. . . . . . . . . . . . . . . . . . . . . 153
6.4.2 MOS capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
6.4.3 Metal-insulator-metal (MIM) capacitors . . . . . . 163
6.4.4 Lateral flux capacitors. . . . . . . . . . . . . . . . . . . . . . 165
6.4.5 Comparison of on-chip decoupling capacitors . . 169
6.5 On-chip switching voltage regulator . . . . . . . . . . . . . . . 171
6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
7 On-Chip Power Distribution Networks . . . . . . . . . . . . 175
7.1 Styles of on-chip power distribution networks . . . . . . . 176
7.1.1 Basic structure of on-chip power distribution networks . . . . . . . . . . . . . . . . . . . . . . 176
7.1.2 Improving the impedance characteristics of
on-chip power distribution networks . . . . . . . . . . 181
7.1.3 Evolution of power distribution networks in
Alpha microprocessors . . . . . . . . . . . . . . . . . . . . . 182
7.2 Die-package interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
7.3 Other considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8 Computer-Aided Design and Analysis . . . . . . . . . . . . . 193
8.1 Design flow for on-chip power distribution networks . 194
8.2 Linear analysis of power distribution networks . . . . . . 199
8.3 Modeling power distribution networks . . . . . . . . . . . . . 201
8.4 Characterizing the power current requirements
of on-chip circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
8.5 Numerical methods for analyzing power distribution networks . . . . . . . . . . . . . . 210
8.6 Allocation of on-chip decoupling capacitors . . . . . . . . . 217
8.6.1 Charge-based allocation methodology . . . . . . . . 218
8.6.2 Allocation strategy based on the excessive noise amplitude . . .. . . . . . . . . . 220
8.6.3 Allocation strategy based on excessive charge . 221
8.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
9 Inductive Properties of On-Chip Power Distribution Grids . . . . . . . . . . . . . . . . . . . 225
9.1 Power transmission circuit . . . . . . . . . . . . . . . . . . . . . . . . 225
9.2 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
9.3 Grid types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
9.4 Inductance versus line width . . . . . . . . . . . . . . . . . . . . . . 233
9.5 Dependence of inductance on grid type . . . . . . . . . . . . 234
9.5.1 Non-interdigitated versus interdigitated grids . . 234
9.5.2 Paired versus interdigitated grids . . . . . . . . . . . . 235
9.6 Dependence of Inductance on grid dimensions . . . . . . . 236
9.6.1 Dependence of inductance on grid width . . . . . . 236
9.6.2 Dependence of inductance on grid length . . . . . 238
9.6.3 Sheet inductance of power grids . . . . . . . . . . . . . 238
9.6.4 Efficient computation of grid inductance . . . . . . 239
9.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
10 Variation of Grid Inductance with Frequency . . . . . 243
10.1 Analysis approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
10.2 Discussion of inductance variation . . . . . . . . . . . . . . . . . 245
10.2.1 Circuit models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
10.2.2 Analysis of inductance variation . . . . . . . . . . . . . 248
10.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
11 Inductance/Area/Resistance Tradeoffs . . . . . . . . . . . . 253
11.1 Inductance vs. resistance tradeoff under a constant grid
area constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
11.2 Inductance vs. area tradeoff under a constant grid
resistance constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
11.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
12 Scaling Trends of On-Chip Power Distribution Noise . . .. . . . . . . . . . . . . . . . . . . 263
12.1 Prior work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

12.2 Interconnect characteristics . . . . . . . . . . . . . . . . . . . . . . . 266
12.2.1 Global interconnect characteristics . . . . . . . . . . . 268
12.2.2 Scaling of the grid inductance . . . . . . . . . . . . . . . 268
12.2.3 Flip-chip packaging characteristics . . . . . . . . . . . 269
12.2.4 Impact of on-chip capacitance . . . . . . . . . . . . . . . 271
12.3 Model of power supply noise . . . . . . . . . . . . . . . . . . . . . . 272
12.4 Power supply noise scaling . . . . . . . . . . . . . . . . . . . . . . . 274
12.4.1 Analysis of constant metal thickness scenario . . 274
12.4.2 Analysis of the scaled metal thickness scenario 275
12.4.3 ITRS scaling of power noise . . . . . . . . . . . . . . . . . 277
12.5 Implications of noise scaling . . . . . . . . . . . . . . . . . . . . . . 281
12.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
13 Impedance Characteristics of Multi-Layer Grids . . 285
13.1 Electrical properties of multi-layer grids . . . . . . . . . . . . 287
13.1.1 Impedance characteristics of individual grid layers . . . . . .. . . . . . . . . . . . 287
13.1.2 Impedance characteristics of multi-layer grids . 290
13.2 Case study of a two layer grid . . . . . . . . . . . . . . . . . . . . 292
13.2.1 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . 293
13.2.2 Inductive coupling between grid layers . . . . . . . . 293
13.2.3 Inductive characteristics of a two layer grid . . . 297
13.2.4 Resistive characteristics of a two layer grid . . . . 298
13.2.5 Variation of impedance with frequency in a two layer grid . . . . . . . . . . . . . . . . 300
13.3 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
13.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
14 Multiple On-Chip Power Supply Systems . . . . . . . . . 305
14.1 ICs with multiple power supply voltages . . . . . . . . . . . 306
14.1.1 Multiple power supply voltage techniques . . . . . 307
14.1.2 Clustered voltage scaling (CVS) . . . . . . . . . . . . . 309
14.1.3 Extended clustered voltage scaling (ECVS) . . . 310
14.2 Challenges in ICs with multiple power supply voltages 311
14.2.1Die area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
14.2.2 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 312
14.2.3 Design complexity . . . . . . . . . . . . . . . . . . . . . . . . . 313
14.2.4 Placement and routing . . . . . . . . . . . . . . . . . . . . . 313
14.3 Optimum number and magnitude of available power supply voltages . . . . . .. . . . . . . . . . 316
14.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
15 On-Chip Power Distribution Grids with Multiple Supply Voltages . . . . . . . . . . 323
15.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
15.2 Simulation setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
15.3 Power distribution grid with dual supply and dual ground. . . . . . . . . . . . . . . .
. . . . . . 328
15.4 Interdigitated grids with DSDG . . . . . . . . . . . . . . . . . . . 331
15.4.1Type I interdigitated grids with DSDG . . . . . . . 331
15.4.2Type II interdigitated grids with DSDG . . . . . . 333
15.5 Paired grids with DSDG . . . . . . . . . . . . . . . . . . . . . . . . . 335
15.5.1 Type I paired grids with DSDG . . . . . . . . . . . . . 336
15.5.2 Type II paired grids with DSDG. . . . . . . . . . . . . 337
15.6 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
15.6.1 Interdigitated power distribution grids without decoupling capacitors . . .. . . . . . . . . . 341
15.6.2 Paired power distribution grids without decoupling capacitors . . . . . . . . . . 348
15.6.3 Power distribution grids with decoupling capacitors . . . . . . . . . . . . . . . 349
15.6.4 Dependence of power noise on the switching frequency of the current loads .. . . . 353
15.7 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
15.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
16 Decoupling Capacitors for Multi-Voltage Power Distribution Systems . . . . . . . . . . 361
16.1 Impedance of a power distribution system . . . . . . . . . . 363
16.1.1 Impedance of a power distribution system . . . . 364
16.1.2 Antiresonance of parallel capacitors . . . . . . . . . . 367
16.1.3 Dependence of impedance on power distribution system parameters . . . . .. . . . 368
16.2 Case study of the impedance of a power distribution system. . . . . .. . . . . . . . . . 371
16.3 Voltage transfer function of power distribution system 376
16.3.1 Voltage transfer function of a power distribution system . . .. . . . . . . . . . . . . . . . . 376
16.3.2 Dependence of voltage transfer function on power distribution system parameters .. . . . 378


16.4 Case study of the voltage response of a power distribution system .
. . . . . . . 381
16.4.1 Overshoot-free magnitude of a voltage transfer function . .
. . . . . . . . . . . . . 383
16.4.2 Tradeoff between the magnitude and frequency range . . . . .
. . . . . . . . . . . . . . . 385
16.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
17 On-chip Power Noise Reduction Techniques in High Performance ICs .
. . . 391
17.1 Ground noise reduction through an additional low noise on-chip ground.
. . . . . . . . . . 393
17.2 Dependence of ground bounce reduction on system parameters . . . . . . . . . . . . . . . . . . 395
17.2.1 Physical separation between noisy and noise sensitive circuits . . . . . . . . . . . . 396
17.2.2 Frequency and capacitance variations . . . . . . . . 397
17.2.3 Impedance of an additional ground path . . . . . . 399
17.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
18 Effective Radii of On-Chip Decoupling Capacitors 403
18.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
18.2 Effective radius of on-chip decoupling capacitor based on a target impedance . . . . . . . . . 407
18.3 Estimation of required on-chip decoupling capacitance 409
18.3.1Dominant resistive noise . . . . . . . . . . . . . . . . . . . . 410
18.3.2 Dominant inductive noise . . . . . . . . . . . . . . . . . . . 411
18.3.3Critical line length . . . . . . . . . . . . . . . . . . . . . . . . . 414
18.4 Effective radius as determined by charge time . . . . . . . 416
18.5 Design methodology for placing on-chip decoupling capacitors
. . . . . . . . . . . . . . . 422
18.6 Model of on-chip power distribution network . . . . . . . . 422
18.7 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
18.8 Design implications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
18.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
19 Efficient Placement of Distributed On-Chip Decoupling Capacitors
. . . . . . . . . . 435
19.1 Technology constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
19.2 Placing on-chip decoupling capacitors in nanoscale ICs 437
19.3 Design of a distributed on-chip decoupling capacitor network
. . . . . . . . . . . . . 440
19.4 Design tradeoffs in a distributed on-chip decoupling capacitor network

. . . . . . . . . 445
19.4.1 Dependence of system parameters on R1 . . . . . . 446
19.4.2 Minimum C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
19.4.3 Minimum total budgeted on-chip decoupling capacitance . . . . . . . . . . . . . . . 448
19.5 Design methodology for a system of distributed on-chip decoupling capacitors
. . . . . . . 450
19.6 Case study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
20 Impedance/Noise Issues in On-Chip Power Distribution Networks
. . . . . . . . 459
20.1 Scaling effects in chip-package resonance . . . . . . . . . . . 460
20.2 Propagation of power distribution noise . . . . . . . . . . . . 463
20.3 Local inductive behavior . . . . . . . . . . . . . . . . . . . . . . . . . 465
20.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
21 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
Appendices
A Mutual Loop Inductance in Fully Interdigitated
Power Distribution Grids with DSDG. . . . . . . . . . . . . 477
B Mutual Loop Inductance
in Pseudo-Interdigitated Power Distribution Grids with DSDG . . . . . . . . . . 479
C Mutual Loop Inductance in Fully Paired Power
Distribution Grids with DSDG. . . . . . . . . . . . . . . . . . . . 481
D Mutual Loop Inductance in Pseudo-Paired Power
Distribution Grids with DSDG. . . . . . . . . . . . . . . . . . . . 483
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509