Clock Domain Crossing (CDC) Design

sysclock

SolvNet的最新文章。
Important design considerations require that multi-clock designs be carefully constructed at
Clock Domain Crossing (CDC) boundaries. This paper details some of the latest strategies and
best known methods to address passing of one and multiple signals across a CDC boundary.
Included in the paper are techniques related to CDC verification and an interesting 2-deep FIFO
design for passing multiple control signals between clock domains. Although the design methods
described in the paper can be generally implemented using any HDL, the examples are shown
using efficient SystemVerilog techniques.

sysclock

The attached PDF file describes the 45-nm design rules supported in
IC Compiler version B-2008.09.

sysclock

The create_testcase script is a Tcl procedure that assists in packaging a database for a STAR. This procedure supports only IC Compiler and Design Compiler (the support for Design Compiler is currently in beta and does not support topological mode).
The procedure obtains and archives all the necessary database files  to be used by IC Compiler or Design Compiler for generating a testcase.  You need to modify a template script that is used to generate and reproduce the actual flow, based on the input database saved and archived by this utility.  The create_testcase script does not try to capture the actual scripts or files used by a script. It is designed to be independent of the script system, capture reference data, and createa database that can be opened in any directory.
The create_testcase script

• Supports Milkyway format for IC Compiler
• Supports .ddc format for Design Compiler create_testcase.tcl.txt (40.5 KB, 下载次数: 13 )
  2008-10-5 11:17 上传

  点击文件名下载附件

jcchan

很好的資料，感謝大大無私的分享。

johnsonlin

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jjw3310

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armmips

Thanks for sharing.

armmips

Thanks for sharing.