如何检测信号的上升沿?

awetman

//上升沿检测模块,要求信号保持时间在一个clock周期以上
module rising_edge_check(clock, signal, rising_flag);
    input clock;
    input signal;//input signal
    output rising_flag;//rising edge flag
reg [2:0] temp=3'b000;
always @(posedge clock)
  temp<={temp[1:0],signal};
assign rising_flag=(temp[1:0]==2'b01)?1'b1:1'b0;
endmodule
//testbench
module test_rising_edge_check_v;
// Inputs
reg clock;
reg signal;
// Outputs
wire rising_flag;
// Instantiate the Unit Under Test (UUT)
rising_edge_check uut (
  .clock(clock),
  .signal(signal),
  .rising_flag(rising_flag)
);
initial begin
  // Initialize Inputs
  clock = 0;
  signal = 0;
  // Wait 100 ns for global reset to finish
  #100;
        
  // Add stimulus here
  signal=1;
  #500;
  signal=0;
  #500;
  signal=1;
  #200;
  signal=0;
  #100;
  signal=1;
  #300;
  signal=0;
end
   always #100 clock=~clock   ;
endmodule

kangrx

temp<={temp[1:0],signal};
请问这条语句是什么意思

yangyuanwei

还是有收获的