|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
The reference is too big, only load the presentation here. T9 is too big, removed from the package.
T1: Fundamentals of Class-D Amplifier Operation & Design
Class-D amplifiers, due to their high efficiencies, are extremely attractive for integrated
and low power applications where long battery life and reduced heat are crucial. This
tutorial begins with a brief overview of architectures and system concerns and is
followed by detailed explanations of the issues found in the typical class-D design
process. We will conclude with some insights into the current state of the art as well as
what the future might hold in this area.
T2: Pipelined A/D Converters: The Basics
For resolutions from 8- to 14-bits at speeds from 1MS/s to greater than 1GS/s,
pipelined ADCs have become the ADC architecture of choice. This tutorial starts with
the basics. A spatial analogy is used to explain sub-ranging and redundancy leading to
a simple intuitive understanding of all such architectures, including non-radix-two
successive approximation ADCs. Key circuit-design issues will be addressed, such as
amplifier requirements and device sizing for noise and matching constraints. These
concepts will then be applied in the context of a generic design example of a 10-bit
ADC.
T3: CMOS Temperature Sensors
CMOS temperature sensors are everywhere! They are used in CPUs for thermal
management, in DRAMs to control refresh rates, and in MEMS frequency references
for temperature compensation, to name a few high-volume applications. In this tutorial,
the operating principles of CMOS temperature sensors will be explained, their main
sources of inaccuracy identified, and suitable remedies, at the device, circuit and
system levels, described. To further illustrate these concepts, the design of a state-ofthe-
art CMOS temperature sensor with an inaccuracy of less than 0.1°C over the
military temperature range (–55°C to 125°C) will be presented.
T4: SoC Power-Reduction Techniques
Power consumption is and continues to be the hottest topic for battery-operated
portable devices. This tutorial provides a comprehensive overview of most commonly
adopted Digital CMOS Leakage Reduction and Power-Management techniques. It also
presents the benefits of those techniques and their realization at all phases of the IC
design process, from system architecture to physical implementation. What is DVFS?
What does power gating mean? How can massive clock gating help to reduce leakage?
How to apply low power techniques to SRAM design? How can system architectures
help? These are among the questions that will be answered during this tutorial.
T5: Digital Phase-Locked Loops
Phase-locked loop (PLL) circuits are a key component of most modern communication
circuits, and are also used in a variety of digital processor applications in order to
generate high-frequency low-jitter clock sources. Here, we examine the issue of
achieving digital implementation of these structures with the aim of achieving excellent
noise performance. Basic concepts of classical analog PLL structures will first be
examined, followed by an overview of digital PLL structures and their associated circuit
implementation issues. Higher level design and simulation techniques are presented, as
well as several case studies of implemented examples.
T6: Leakage-Reduction Techniques
CMOS technology scaling in sub-100nm range comes with increased transistor
leakage. To continue harvesting technology scaling benefits, it is essential for circuit
designers and system architects to understand the nature and impact of leakage, its
sensitivity to different design parameters, and practical techniques to reduce it. This
tutorial will review process and circuit design techniques for leakage reduction with
examples from 65nm and 90nm designs from the industry as well as academic
research. Special emphasis will be devoted to power gating techniques, the equivalent
of clock gating for local leakage mitigation.
T7: NAND Memories for SSD
The NAND-flash-memory-based solid-state disk (SSD) for PC applications has attracted
a lot of attention as the cost of NAND flash memory drastically reduces. To realize a
high performance and highly reliable SSD, it is essential to understand SSD from a
broad perspective such as device, circuit, system architecture and operating system.
This tutorial covers the following topics to provide a comprehensive view of SSD.
• NAND device/circuit basic operation
• SSD overview such as market, cost, reliability, performance, power consumption.
• NAND circuit design for SSD
• NAND controller design for SSD
• Operation system for SSD
T8: Silicon mm-Wave Circuits
A recent surge of interest in Si mm-wave circuits and systems, evidenced by the
number of conference/journal papers and new research organizations, clearly
demonstrates keen interest in exploring new applications for mm-wave frequencies.
The design of circuits above 30GHz poses unique challenges and requires new design
methodology, often outside the realm of the analog circuit designer’s background and
skill set. This tutorial will review fundamental theory and practical techniques applicable
to mm-wave circuits. The design of key building blocks such as amplifiers, mixers, and
oscillators will be discussed incorporating Si transmission-line techniques, matching
circuits, and distributed elements.
T10: Basics of High-Speed Chip-to-Chip and Backplane Signaling
This tutorial presents the basics of high-speed transceivers with emphasis on circuit
design requirements for chip-to-chip and backplane signaling. The topics include
channel characterization and equalization, MUX and DEMUX design, decision circuits,
as well as clock- and data-recovery (CDR) circuits and concepts. Approximately half of
the tutorial will be devoted to I/O blocks and half to CDR. The goal of the tutorial is to
help the audience absorb the related papers presented at the conference.
[ 本帖最后由 casdvo 于 2008-9-8 12:59 编辑 ] |
-
-
Tutorial08.part1.rar
4.25 MB, 下载次数: 1044
, 下载积分:
资产 -3 信元, 下载支出 3 信元
-
-
Tutorial08.part2.rar
4.25 MB, 下载次数: 936
, 下载积分:
资产 -3 信元, 下载支出 3 信元
-
-
Tutorial08.part3.rar
4.25 MB, 下载次数: 956
, 下载积分:
资产 -3 信元, 下载支出 3 信元
-
-
Tutorial08.part4.rar
4.25 MB, 下载次数: 923
, 下载积分:
资产 -3 信元, 下载支出 3 信元
|