用modelsim做综合布线后的仿真出现了问题！

lizhen7799

在quartusII里综合布线后，用modelsim出现以下的错误：
# Top level modules:
# test_counter
vsim -sdftyp /=E:/quartus/counter/simulation/modelsim/counter_v.sdf work.test_counter
# vsim -sdftyp /=E:/quartus/counter/simulation/modelsim/counter_v.sdf work.test_counter
# Loading D:/Modeltech_ae/win32aloem/../win32aloem/convert_hex2ver.dll
# Loading work.test_counter
# Loading work.counter
# ** Warning: (vsim-3010) [TSCALE] - Module 'counter' has a `timescale directive in effect, but previous modules do not.
#         Region: /test_counter/dut
# Loading work.cyclone_io
# Loading work.mux21
# Loading work.dffe
# Loading work.cyclone_asynch_io
# Loading work.cyclone_lcell
# Loading work.cyclone_asynch_lcell
# Loading work.cyclone_lcell_register
# ** Warning: (vsim-3006) E:/quartus/counter/simulation/modelsim/tcounter.v(6): [TMIPA] - Too many inherited module instance parameters.
#         Region: /test_counter
# ** Warning: (vsim-3015) E:/quartus/counter/simulation/modelsim/tcounter.v(6): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'clk'.
#         Region: /test_counter/dut
# ** Error: (vsim-3053) E:/quartus/counter/simulation/modelsim/tcounter.v(6): Illegal output port connection (port 'count').
#         Region: /test_counter/dut
# ** Warning: (vsim-3015) E:/quartus/counter/simulation/modelsim/tcounter.v(6): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'count'.
#         Region: /test_counter/dut
# Loading work.PRIM_DFFE
# Error loading design
各位能不能解析一下，这种情况怎么解决啊！

bravelu

好像是端口不匹配，前仿真做过了？

lizhen7799

有啊！！都是正确的啊

一声叹息

我看你在调用SDF时他的作用范围是root（vsim -sdftyp =/），但调用的仿真文件是TestBench。我想SDF应该作用于你要测试的模块（可能是你的Counter）。
是不是这个原因呀？

bravelu

不太像，好像编译的进程还没到反标sdf就报错了。

lizhen7799

我的测试模块是test_counter.v,sdf指定在测试模块上了。
现在把这个程序和测试模块贴出来，希望各位帮忙分析一下
module counter (count, clk, rst);
output [7:0] count;
input clk, rst;
reg [7:0] count;
parameter tpd_clk_to_count   =  1;
parameter tpd_reset_to_count =  1;

function [7:0] increment;
input [7:0] val;
reg [3:0] i;
reg carry;
  begin
    increment = val;
    carry = 1'b1;
    /*
     * Exit this loop when carry == zero, OR all bits processed
     */
    for (i = 4'b0; ((carry == 4'b1) || (i <= 7));  i = i+ 4'b1)
       begin
         increment = val ^ carry;
         carry = val & carry;
       end
  end      
endfunction
/*****************************************************************
* The following always block was changed to make it synthesizable.
always @ (posedge clk or posedge rst)
  if (rst)
     count = #tpd_reset_to_count 8'h00;
  else
     count <= #tpd_clk_to_count increment(count);
******************************************************************/
always @ (posedge clk or posedge rst)
  if (rst)
     count = 8'h00;
  else
     count <= count + 8'h01;
   
endmodule

测试文件
module test_counter;
reg clk, rst;
wire [7:0] count;
counter counter1(count,clk,rst);// #(5,10) counter (count,clk,rst);
initial // Clock generator
  begin
    clk = 0;
    #10 forever #10 clk = !clk;
  end
  
initial// Test stimulus
  begin
    rst = 0;
    #5 rst = 1;
    #4 rst = 0;
    #50000 $stop;
  end
  
initial
    $monitor($stime,, rst,, clk,,, count);
   
endmodule   

lizhen7799

把测试文件修改了一下：
`timescale 1 ns / 1 ps
module test_counter;
reg clk, rst;
wire [7:0] count;
counter counter1(.count(count),.clk(clk),.rst(rst));// #(5,10) counter (count,clk,rst);
initial // Clock generator
  begin
    clk = 0;
    #10 forever #10 clk = !clk;
  end
  
initial// Test stimulus
  begin
    rst = 0;
    #5 rst = 1;
    #4 rst = 0;
    #50000 $stop;
  end
  
initial
    $monitor($stime,, rst,, clk,,, count);
   
endmodule   
就出现这种错误：

# test_counter
vsim -sdftyp /test_counter=E:/quartus/counter/simulation/modelsim/counter_v.sdo work.test_counter
# vsim -sdftyp /test_counter=E:/quartus/counter/simulation/modelsim/counter_v.sdo work.test_counter
# Loading D:/Modeltech_ae/win32aloem/../win32aloem/convert_hex2ver.dll
# Loading work.test_counter
# Loading work.counter
# Loading work.cyclone_io
# Loading work.mux21
# Loading work.dffe
# Loading work.cyclone_asynch_io
# Loading work.cyclone_lcell
# Loading work.cyclone_asynch_lcell
# Loading work.cyclone_lcell_register
# Loading work.PRIM_DFFE
# ** Fatal: SDF files require Altera primitive library
#    Time: 0 ps  Iteration: 0  Instance: /test_counter File: E:/quartus/counter/simulation/modelsim/test_counter.v
# FATAL ERROR while loading design
# Error loading design

一声叹息

将仿真加载命令改成如下形式试试：
vsim -L altera_lib -sdftyp /counter1=E:/quartus/counter/simulation/modelsim/counter_v.sdo work.test_counter
其中(altera_lib)为altera的仿真库，例如：如果你使用stratix器件，就是stratix_ver

lizhen7799

谢谢一声叹息！！
    用你的上面所说的加载命令，问题解决了，但是有一个问题还是想一下，我用的GUI模式来操作为什么不行啊，而用Comand Line模式就可以啊！用GUI模式时，我是按照别人介绍的方法把仿真库拷到工程文件夹下，然后编译，进行装载的，就出现了以上的错误。为什么会这样啊！！具体的操作步骤是照datasheet来做的。能不能谈谈GUI与Command Line的区别啊！！

一声叹息

GUI与Command Line应该没有区别。你在编译仿真库时是不是出错了。
从现象看在调用PRIM_DFFE出错，见你的出错信息：
# Loading work.PRIM_DFFE
# ** Fatal: SDF files require Altera primitive library
#    Time: 0 ps  Iteration: 0  Instance: /test_counter file: E:/quartus/counter/simulation/modelsim/test_counter.v
# FATAL ERROR while loading design
# Error loading design