IEEE JSSC 2007-2008 有关memory 的papers

corespirit36

这些囊括了2007-2008 JSSC上所有的关于memory的Papers。
文件太大了，都是上MB的，所以我尽量把好几个Papers压缩在一个文件中，附上文件名，大家看好后再下载吧。
P.S. 各个压缩文件互相独立，可以独立下载。

Part1：
memory_1.rar (4.33 MB, 下载次数: 72 )

2008-7-18 00:11 上传

点击文件名下载附件

1.   2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

2.   A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

corespirit36

Part2：
对不住了，下面两个压在一起超过了限制，分开好了，大家多花点银子了。。。

abbr_0f197e0501d5d211f2e3ab891cfcf197.pdf (2.35 MB, 下载次数: 41 )

2008-7-18 00:19 上传

点击文件名下载附件

corespirit36

Part2：
对不住大家了，我在压缩的时候没有注意，下面两个压在一起超过限制了，分开来吧，大家多花银子了，抱歉！

abbr_0f197e0501d5d211f2e3ab891cfcf197.pdf (2.35 MB, 下载次数: 37 )

2008-7-18 00:25 上传

点击文件名下载附件

corespirit36

上两个的论文是一样的，论文名字是：　
A 1.1 GHz 12 uA per Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology with Integrated Leakage Reduction for Mobile Applications

Abstract:
Abstract—A low-power, high-speed SRAM macro is designed
in a 65 nm ultra-low-power (ULP) logic technology for mobile
applications. The 65 nm strained silicon technology improves
transistor performance/leakage tradeoff, which is essential to
achieve fast SRAM access speed at substantially low operating
voltage and standby leakage. The 1 Mb SRAM macro features
a 0.667 m2 low-leakage memory cell and can operate over a
wide range of supply voltages from 1.2 V to 0.5 V. It achieves
operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V,
respectively. The SRAM leakage is reduced to 12 A/Mb at the
data retention voltage of 0.5 V. The measured bitcell leakage from
the SRAM array is 2 pA/bit at retention voltage with integrated
leakage reduction schemes.

corespirit36

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Abstract:
The variation tolerant assist circuits of an SRAM
against process and temperature are proposed. Passive resistances
are introduced to the read assist circuit with replica memory
transistors to lower the wordline voltage accurately reflecting the
process and temperature variations. For the sake of not only enlarging
the write margin but also reducing power consumption and
speed overhead, the divided dynamic power-line scheme based on
a charge sharing is adopted. Test chips of 512-Kb SRAM macros
and isolated memory cell TEGs are fabricated using 45-nm bulk
CMOS technology. Two types of 6-T SRAM cells, whose sizes were
0.245 um2 and 0.327 um2 were designed and evaluated. From
the measurement results, we achieved over 100-mV improvement
for static noise margin, and 35 mV for write margin for both
SRAM cells at 1.0-V worst condition by using assist circuitry. It
enables the wordline level to keep higher voltage at the slowest
condition than the typical process condition, which results in 83%
improvement of the cell current compared with the conventional
assist circuit. Furthermore, the minimum operating voltage in the
worst case condition was improved by 170 mV, confirming a high
immunity against process and temperature variations with less
than 10% area overhead.

abbr_c588f7daa249baf526c3d3a6efde6a57.pdf (2.65 MB, 下载次数: 45 )

2008-7-18 00:28 上传

点击文件名下载附件

corespirit36

Part3：

1   A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous RW Access Issues

2   A 65 nm 1 Gb 2b per cell NOR Flash With 2.25 MB per s Program Throughput and 400 MB per s DDR Interface

3   Memory at VLSI Circuits Symposium

memory_3.rar (4.51 MB, 下载次数: 65 )

2008-7-18 00:33 上传

点击文件名下载附件

这次附件应该不会超过限制了吧。。。

corespirit36

Part4

1   A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

2   An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

memory_4.rar (4.86 MB, 下载次数: 41 )

2008-7-18 00:35 上传

点击文件名下载附件

corespirit36

Part5

1   A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

2   Embedded SRAM circuit design technologies for a 45nm and beyond

memory_5.rar (4.68 MB, 下载次数: 52 )

2008-7-18 00:36 上传

点击文件名下载附件

corespirit36

Part6
这次又超过了，本人第一次上传，真是对不住大家啊，老是超过限制大小。再分开吧

A Low-Power SRAM Using Bit-Line Charge-Recycling
A Low-Power SRAM Using Bit-Line Charge-Recycling.pdf (1.67 MB, 下载次数: 49 )

2008-7-18 00:39 上传

点击文件名下载附件

corespirit36

Part6

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

abbr_64995f6dc7ac60bbff175a25bfae20f5.pdf (3.5 MB, 下载次数: 32 )

2008-7-18 00:41 上传

点击文件名下载附件

不知道为什么上传后名字会变，我给出Paper的名字吧

还有Abstract
A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM)
chip using a 0.2 um logic process with an MgO tunneling barrier
cell demonstrates the circuit technologies for potential lowpower
nonvolatile RAM, or universal memory. This chip features
an array scheme with bit-by-bit bi-directional current writing to
achieve proper spin-transfer torque writing of 100 ns, and parallelizing-
direction current reading with a low-voltage bit-line for
preventing read disturbances that lead to 40 ns access time.