ESD 参考文献，收藏1

hzfeiyun

索引，先占个位置，后面慢慢加

[ 本帖最后由 hzfeiyun 于 2008-7-4 12:37 编辑 ]

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BASIC ESD AND I/O DESIGN

Basic ESD and I/O Designby Sanjay Dabral (Author), Timothy Maloney (Author)

Hardcover: 328 pages Publisher: Wiley-Interscience; 1 edition (November 30, 1998) Language: English
PDF 文档，扫描版的

内容介绍：

Product Description
The first comprehensive guide to ESD protection and I/O design
Basic ESD and I/O Design is the first book devoted to ESD (electrostatic discharge) protection and input/output design. Addressing the growing demand in industry for high-speed I/O designs, it bridges the gap between ESD research and current VLSI design practices and provides a much-needed reference for practicing engineers who are frequently called upon to learn the subject on the job. This volume presents an integrated treatment of ESD, I/O, and process parameter interactions that both I/O designers and process designers can use. It examines key factors in I/O and ESD design and testing, and helps the reader consider ESD and reliability issues up front when making I/O choices. Emphasizing clarity and simplicity, this book focuses on design principles that can be applied widely as this dynamic field continues to evolve. Basic ESD and I/O Design:

• Describes strategies for design-oriented ESD protection
• Explains layout methods that enhance ESD protection designs
• Addresses basic I/O designs, including new problems such as mixed voltage interfaces
• Discusses fabrication aspects affecting ESD and I/O protection
• Illustrates concepts using numerous figures and examples
• Expresses device physics in terms of simple electrical circuit models
• Cross-references the material to standard texts in the field

Essential for engineers in industry and anyone designing circuits, systems, or devices for future technologies, Basic ESD and I/O Design is also a useful reference for researchers and graduate students involved in core VLSI design or computer architecture.

Book Info
Devoted to ESD (electrostatic discharge) protection and input/output (I/O) design. Addresses the growing demand in industry for highspeed I/O designs, bridging the gap between ESD research and current VLSI design practices and provides a reference for practicing engineers. DLC: Integrated circuits--Very large scale integration--protection.


详细内容可参考http://www.amazon.com/Basic-ESD-I-O-Design/dp/0471253596

[ 本帖最后由 hzfeiyun 于 2008-7-4 11:43 编辑 ]

hzfeiyun

機器放電模式之全晶片靜電放電防護

王泰和，凌陽科技股份有限公司
摘要：16 Mbit 的可規劃罩冪式記憶體(programmable mask ROM)積體電路(integrated circuits,
IC)產品，在本公司內部機台測試結果，機器模式(machine model, MM)靜電放電(electrostatic
discharge, ESD)耐受度可達300 V，但在客戶端的測試結果卻只有150 V。經過詳細的分析，
我們發現機器模式靜電放電的結果和輸出波形的速度有相當大的關係。如果速度很快時，將
會造成晶片內部電路的破壞。新的設計架構針對此問題進行修正改良，並成功地改善該產品
機器模式的靜電放電耐受度至350 V 的水準。

hzfeiyun

Noise-Constrained Design of Reliable Power Networks for Mixed-Power Supply Systems

Jaesik Lee
University of Illinois, Urbana, IL
jslee@mail.icims.csl.uiuc.edu

Sung-Mo (Steve) Kang
University of California, Santa Cruz, CA
kang@cse.ucsc.edu

hzfeiyun

ESD Reliability Issues in RF CMOS Circuits
M.K. Radhakrishnan
Consultant, 660, 05-481, Singapore 530660.
V. Vassilev, B. Keppens , V. De Heyn, M. Natarajan, and G. Groeseneken
IMEC vzw, 75 Kapeldreef, Leuven, Belgium 3001.

hzfeiyun

Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit
Design in Deep Submicron CMOS Processes
Ajith Amerasekera, Charvaka Duvvury, Vij ay Reddy, Mark Rodder
Semiconductor Process and Device Center, Texas Instruments Inc.
MS 461, P.O. Box 655012, Dallas, TX 75265.

hzfeiyun

ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process
Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, and Wen-Yu Lo*
Integrated Circuits & Systems Laboratory
Institute of Electronics
National Chiao-Tung University, Taiwan

* Design Technology Development Division
Silicon Integrated Systems (SiS) Corp.
Science-Based Industrial Park, Hsinchu, Taiwan

[ 本帖最后由 hzfeiyun 于 2008-7-4 12:36 编辑 ]

hotlip1

缺的就是这一个。

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