不好意思，只能全都搬上来了!^o^

dragontan

不好意思，只能全都搬上来了，请大家指正！
芯片XC95144,开发环境ISE 4.1iWebPACK
我用Vrerilog写了几个模块，分别编译的时候都通过了，然后Create Schematic Symbol,但是用XilinxECS把几个模块连接起来后，综合失败，综合的报告如下，不好意思，有点长，都是苍蝇字，我也不知道问题出在哪里！请高手过目，叩拜！~~~
Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s

--> Parameter overwrite set to YES
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s

--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : sch_1107.prj
---- Target Parameters
Target Device                      : XC9500
Output File Name                   : sch_1107
Output Format                      : NGC
Target Technology                  : 9500
---- Source Options
Top Module Name                    : sch_1107
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES
---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES
---- Other Options
wysiwyg                            : NO
=========================================================================

Compiling source file : sch_1107.prj
Compiling included source file 'WrToRam.v'
Module <WrToRam> compiled.
Continuing compilation of source file 'sch_1107.prj'
Compiling included source file 'sp_creator.v'
Module <sp_creator> compiled.
Continuing compilation of source file 'sch_1107.prj'
Compiling included source file 'RdFrRam.v'
Module <RdFrRam> compiled.
Continuing compilation of source file 'sch_1107.prj'
Compiling included source file 'sch_1107.vf'
Module <sch_1107> compiled.
Continuing compilation of source file 'sch_1107.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'sch_1107.prj'
No errors in compilation
Analysis of file <sch_1107.prj> succeeded.


Starting Verilog synthesis.

Analyzing module <WrToRam>.
WARNING:Xst:854 - "WrToRam.v", line 19: Ignored initial statement.
Module <WrToRam> is correct for synthesis.

Analyzing module <sp_creator>.
WARNING:Xst:854 - "sp_creator.v", line 8: Ignored initial statement.
Module <sp_creator> is correct for synthesis.

Analyzing module <RdFrRam>.
Module <RdFrRam> is correct for synthesis.

Analyzing top module <sch_1107>.
Module <sch_1107> is correct for synthesis.
Synthesizing Unit <WrToRam>.
    Related source file is WrToRam.v.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 5                                              |
    | Inputs             | 0                                              |
    | Outputs            | 6                                              |
    | Reset type         | synchronous                                    |
    | Encoding           | automatic                                      |
    | State register     | D  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 15-bit tristate buffer for signal <A>.
    Found 1-bit register for signal <Busy>.
    Found 8-bit tristate buffer for signal <D>.
    Found 1-bit register for signal <nWE>.
    Found 15-bit register for signal <Mtridata_A>.
    Found 8-bit register for signal <Mtridata_D>.
    Found 1-bit register for signal <Mtrien_A>.
    Found 1-bit register for signal <Mtrien_D>.
    Summary:
inferred   1 Finite State Machine(s).
inferred  27 D-type flip-flop(s).
inferred  23 Tristate(s).
Unit <WrToRam> synthesized.

Synthesizing Unit <sp_creator>.
    Related source file is sp_creator.v.
WARNING:Xst:646 - Signal <count> is assigned but never used.
WARNING:Xst:646 - Signal <count> is assigned but never used.
    Found 1-bit register for signal <sp_pre>.
WARNING:Xst:644 - Signal <sp_pre> has a multisource.
WARNING:Xst:647 - Input <SEL> is never used.
    Summary:
inferred   1 D-type flip-flop(s).
Unit <sp_creator> synthesized.

Synthesizing Unit <RdFrRam>.
    Related source file is RdFrRam.v.
    Found 15-bit tristate buffer for signal <A>.
    Summary:
inferred  15 Tristate(s).
Unit <RdFrRam> synthesized.

Synthesizing Unit <sch_1107>.
    Related source file is sch_1107.vf.
WARNING:Xst:644 - Signal <A<13>> has a multisource.
WARNING:Xst:644 - Signal <A<12>> has a multisource.
WARNING:Xst:644 - Signal <A<11>> has a multisource.
WARNING:Xst:644 - Signal <A<10>> has a multisource.
WARNING:Xst:644 - Signal <A<9>> has a multisource.
WARNING:Xst:644 - Signal <A<8>> has a multisource.
WARNING:Xst:644 - Signal <A<7>> has a multisource.
WARNING:Xst:644 - Signal <A<6>> has a multisource.
WARNING:Xst:644 - Signal <A<5>> has a multisource.
WARNING:Xst:644 - Signal <A<4>> has a multisource.
WARNING:Xst:644 - Signal <A<3>> has a multisource.
WARNING:Xst:644 - Signal <A<2>> has a multisource.
WARNING:Xst:644 - Signal <A<1>> has a multisource.
WARNING:Xst:644 - Signal <A<0>> has a multisource.
WARNING:Xst:644 - Signal <A<14>> has a multisource.
Unit <sch_1107> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs                             : 1
# Registers                        : 7
  15-bit register                  : 1
  8-bit register                   : 1
  1-bit register                   : 5
# Tristates                        : 3
  15-bit tristate buffer           : 2
  8-bit tristate buffer            : 1
=========================================================================
Selecting encoding for FSM_0 ...
Encoding for FSM_0 is Johnson, flip-flop = D
Starting low level synthesis...
Optimizing unit <sp_creator> ...
WARNING:Xst:92 - Multi-source on signal <sp_pre> not replaced by logic
ERROR:Xst:415 - Synthesis failed
CPU : 2.39 / 2.80 s | Elapsed : 3.00 / 3.00 s

-->

longerzhu

multisource啊
查查是不是不同的always块对同一个寄存器进行赋值

dragontan

问题好像就是出在sp_creator这个模块，对它单独综合不成功！
模块的目的是想做一个SEL下降研触发的单脉冲发生器，源程序如下：
module sp_creator(SEL,CLK,SingleP);
    input SEL;
    input CLK;
    output SingleP;
    reg SingleP;
    reg sp_pre;
    integer count;
initial
   begin
    sp_pre<=0;
SingleP<=0;
count<=0;
end
always@(negedge SEL)
    begin
if(!sp_pre)     //for not engaged in SingleP process保证在SingleP脉冲开始的时候，忽略触发电平SEL
       begin
         sp_pre<=1;
      count<=0;
end
end
always@(posedge CLK)
   if(sp_pre)
    begin
   SingleP<=1;
   count<=count+1;
if(count==3) begin
             SingleP<=~SingleP;
sp_pre<=~sp_pre;
count<=0;
end
end
endmodule
请大家提提意见，我该怎么改？！谢谢！

atuhappy

count在两个always块里赋值

aluzi

initial在DC里不能综合，好像FPGA也是吧？