求助] cadence17.2更新pcb设计报表不成功

bush009

使用cadence从原理图导出设计至PCB图时，运行到第二部 updating pcb editor board 报错：===========================================================
ERROR: Schematic supports automatically creating XNets using DML but the Layout will not automatically create any XNets. Change setting in Layout or Schematic, re-generate files, and re-run the flow.
ERROR: Can't import electrical constraint data (pstcmdb.dat)
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Finished Constraint Update
Time: Sat Sep 10 15:43:25 2016
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近期重装过系统，库路径都对，更新报表brd设计就出错。
错误的关键在于the Layout will not automatically create any XNets.
求大神指点一二。