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本帖最后由 benemale 于 2010-7-10 21:58 编辑
[size=120%]VHDL Coding and Logic Synthesis with Synopsys
By Weng Fook Lee
- Publisher: Academic Press
- Number Of Pages: 392
- Publication Date: 2000-06-24
- ISBN-10 / ASIN: 0124406513
- ISBN-13 / EAN: 9780124406513
- Binding: Hardcover
Product Description:
This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of "synthesis tools" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.
Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.
* First practical guide to using synthesis with Synopsys
* Synopsys is the #1 design program for IC design
Summary: Excellent
Rating: 5
I have four VHDL books right now and this is the best. The other books teach you the entire language set, which is nice, but they fail to mention that only a segment of the language is synthesizable. This book does a great job teaching you how to program with effective VHDL code period. This is very important because it can save you countless hours of code rewriting.
Summary: Not the best vhdl synthesis book
Rating: 2
I found this book to be written in a confusing manner, and full of mistakes. For example, on page 51, the author says that hexadecimal E equals decimal 15. Apparently this is not a typo, because it is repeated on page 52, along with the statement that hexadecimal F equals decimal 16. For the beginner, I recommend Bhasker's vhdl primers. Ashenden's Designer's Guide to VHDL is the gold standard for a comprehensive text on the language itself, although it is skimpy on synthesis.
Summary: A must have for any logic synthesis designer
Rating: 5
I agree with previous author. This book won't let you sleep like the "designer's guide to VHDL" will. I strongly recommend reading this book and then read another excellent book ""Digital Systems Design with VHDL and Synthesis" by "K.C. Chang". However, this book still has weakness, it lacks some detailed info about the sysnthesis tool, such like what is wireload model. Knowing those in a little more detail should help the design in getting better result. Also I am not sure what is the point spending more than 100 pages with all the Appendix such like a list of the std_logic_1164 library and the EDIF files. I would rather having more detail info about the synthesis theory than those listing or take out the listings and cut the price down... .
Summary: Very good book, save your time too
Rating: 5
I bought this book together with the "Designer's Guide to VHDL", And I decided to read the later first. One week ago, I found out I was making a big mistake. This book is wonderful, The author put in clear and necessary information and his experience to make the book thick, rather than putting in verbose explanations. When you read this book, you save your time and get better understand of the language, and you can start writing your own code very soon. I love this book, and it doesn't make me sleepy like the "designer's guide to vhdl" did.
Summary: This Book Is Highly Recommended
Rating: 5
This book is highly recommended for all the students and engineers. It explains synthesis in detail with examples showing the reader how to use Synopsys commands to optimize synthesized designs. Besided that, figures and explanations are also included throughout. So, keep it one for yourself!
[ 本帖最后由 benemale 于 2008-6-28 08:59 编辑 ] |
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发表于 2008-6-28 08:51:25
