【AP 2000 好书】VHDL Coding and Logic Synthesis with Synopsys

lp_junior

thank you very much.

zhouzhib2008

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zhouzhib2008

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zhouzhib2008

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zhouzhib2008

55ddddddddddddddddddddddddddddddddd

lgy747

赞一个！！

guofu2010

guofu2010

mscyc0909

VHDL Coding and Logic Synthesis with Synopsys
=====================================
I VHDL CODING
01 Introduction
02 VHDL Simulation and Synthesis Flow
03 Synthesizable Code for Basic Logic Components
04 SignaIVersusVariable
05 Examples of Complex Synthesizable Code
06 Pipeline Microcontroller Synthesizable Design

II LOGIC SYNTHESISWITH SYNOPSYS
07 Timing Considerations in Design
08 VHDL Synthesis with Timing Constraints
09 GTECH Instantiation
10 DesignWare Library
11 Testability Issues in Synthesis
12 FPGA Synthesis
13 Synthesis Links to Layout
14 Design Guideline to Follow for Efficient Synthesis
15 Appendix A (STD LOGI C 1164 Library)
16 Appendix B (Shifter Synthesis Results)
17 Appendix C (Counter Synthesis Results)
18 Appendix D (Pipeline Microcontroller Synthesis Results Top-Down Compilation)
19 Appendix E (EDIF File of Synthesized Microcontroller Example from Chapter 6)
20 Appendix F (SDF File from Synthesized Microcontroller Example of Chapter 6)

jangyouhua

谢谢！好东西！