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IEEE JSSC 2008年6月
A 0.2–2 Gbs 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-$mu$m CMOS
A 5.4 mW-0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard
A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $mu$m SiGe BiCMOS Technology
A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-$mu$m CMOS
A 40-Gbs Transimpedance Amplifier in 0.18-$mu$m CMOS Technology
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology
A CMOS Ku-Band 4x Subharmonic Mixer
A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-$mu rm g$ Bias Stability and 20-$ murm gsqrt{{hbox{Hz}}}$ Resolution
A Programmable SIMD Vision Chip for Real-Time Vision Applications
A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver
An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-$mu{hbox{m}}$ SiGe BiCMOS Technology
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning
Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling |
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