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Introduction
Simulation and Modeling
Simulation
Modeling
Motivation
Limitations of SPICE
Merits of VHDLAMS
Problem Statement
Summary of Results
Outline of the Thesis
Background
Levels of modeling
Device models
Physical device models
Equivalentcircuit models
SPICE Elemental Models
MOSFET elemental models
First Generation Models
Second Generation Models
Third Generation Models
Related Research
Model Theory and Equations
SPICE Models
ii
Diode Models
Static Model
Large Signal Model
BJT Models
Static Model
Large Signal Model
JFET Models
Static Model
Large Signal Model
MOSFET Models
Static Model
Large Signal Model
VHDLAMS Models
Rules and Guidelines
VHDLAMS Model Set
Diode models
Static model
Large Signal Model
BJT models
static model
Largesignal model
MOSFET models
Static model
Largesignal
JFET models
Static model
Performance Evaluation
Criteria
Evaluation
Conclusions and Future Work
Conclusions
Future Work
Bibliography
A Additional Results
iii
A Factors Eecting SEAMS Execution Time
A Diode Static Model
A Halfwave rectier
A Voltage doubler
A Largesignal model of a diode
A Voltage Doubler
A DC Restorer
A Static Model of BJT
A npn Dierential Amplier
A Output Characteristics of a pnp BJT
A Largesignal Model of a pnp BJT
A pnp Switch
A Output Characteristics of a pchannel JFET
A Static Model of MOSFET
A nMOS inverter
A pMOS inverter
A CMOS inverter
A CMOS buer
A nMOS inverter with largesignal model of nMOS
B VHDLAMS Code
B Package Electrical System
B Signal generators
B Rampwave Generator
B Sinewave generator
B Squarewave Generator
B Input from a File
B Static Model of Diode
B Curve Tracer Circuit
B Halfwave Rectier
B Voltage Doubler
B Largesignal Model of a diode
B Halfwave Rectier
B Voltage Doubler
B DC Restorer
B Static models of npn and pnp BJT
B Curve Tracer Circuit for a npn BJT
B Curve Tracer Circuit for a pnp BJT
iv
B npn Common Emitter Amplier
B npn Dierential Amplier Circuit
B Largesignal models of npn and pnp BJTs
B npn Switch
B pnp Switch
B Static Models of JFET
B Curve Tracer circuit for nchannel JFET
B Curve Tracer arrangement for pchannel JFET
B Static Models for MOSFETS
B NMOS inverter with enhancement NMOS load
B PMOS inverter circuit with depletion PMOS load
B CMOS Inverter
B CMOS Buer Circuit
B Largesignal Models of NMOS and PMOS Transistors
B NMOS inverter with largesignal model of NMOS
B PMOS inverter with Largesignal model of a mos transistor |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2008-6-20 19:12:34
