最近做ADPLL，和大家分享一些资料，

poweron111 · 发表于 2011-2-11 19:48:54

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poweron111 · 发表于 2011-2-11 19:50:35

dddddddd

ouyds001 · 发表于 2011-6-15 21:12:46

谢谢！

jyyang175 · 发表于 2011-7-22 11:18:51

回复 1# ipmsn5

xiexie

mscyc0909 · 发表于 2011-7-28 02:36:29

Paper: A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation
CONCLUSIONS:
In this paper, a 1.9mW portable ADPLL-based frequency synthesizer with wide frequency range, low jitter, and short lock cycle is proposed.
A DCO with features of wide frequency range, and low power consumption is proposed. By using the modified DCDEs, the DCO also has better linearity and PVT variation immunity than the conventional DCO. In addition, a dualmode one-cycle PFD is also presented to reduce the lock cycle time.
In conclusion, with such specifications, the proposed ADPLL-based frequency synthesizer is suitable for high speed clock generation in SoC applications.

mscyc0909 · 发表于 2011-7-28 02:42:27

The 4th article was:
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS ADPLL in 65nm SOI.

calven · 发表于 2011-8-3 18:58:52

KANYIXIA

xiaohutushen · 发表于 2011-8-4 14:56:58

HELPFUL THX

xiaohutushen · 发表于 2011-8-4 15:45:13

VERY GOOD

buildgates · 发表于 2011-8-21 21:36:18

Very useful! Thanks a lot!

最近做ADPLL，和大家分享一些资料，

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