Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers

kool

利用VERILOG A建模
Contents
1 Introduction 2
1.1 Frequency Synthesis 3
1.2 Direct Simulation 3
1.3 When Direct Simulation Fails 4
1.4 Monte Carlo-Based Methods 4
1.5 Predicting Noise in PLLs 5
2 Phase-Domain Model 6
2.1 Small-Signal Stability 9
2.2 Noise Transfer Functions 9
2.3 Noise Model 11
3 Oscillators 12
3.1 Oscillator Phase Noise 12
3.2 Characterizing Oscillator Phase Noise 14
3.3 Phase-Domain Models for the Oscillators 16
4 Loop Filter 17
5 Phase Detector and Charge Pump 17
6 Frequency Dividers 18
6.1 Cyclostationary Noise. 19
6.2 Converting to Phase Noise 20
6.3 Phase-Domain Model for Dividers 21
7 Fractional-N Synthesis 22
8 Jitter 23
8.1 Jitter Metrics 24
8.2 Types of Jitter 26
9 Synchronous Jitter 27
9.1 Extracting Synchronous Jitter 28
10 Accumulating Jitter 30
10.1 Extracting Accumulating Jitter 32
11 Jitter of a PLL 34
12 Modeling a PLL with Jitter 34
12.1 Modeling Driven Blocks 34
12.2 Modeling Accumulating Jitter 36
12.3 VCO Model 37
12.4 Efficiency of the Models 38
13 Simulation and Analysis 44
14 Example 46
15 Conclusion 46
15.1 If You Have Questions 47

cookkoo

这个帖子是要回的，谢谢楼主

foolish

多谢了，
LZ介绍的比较详细啊

gsm123456

Trade-Offs In Analog Circuit Design

just2004

thanks

just2004

thanks a lot for your information.
Good luck

pig

xiexie

kiteinsky

thanks a lot

kg_2001

学习了。谢谢楼主。

tianlinzx

Thank you