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IEEE Standard Definitions and Characterization of Floating Gate Seimiconductor

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发表于 2008-6-11 09:30:44 | 显示全部楼层 |阅读模式

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Contents
1. Overview............................................................................................................................................. 1
1.1 Scope........................................................................................................................................... 1
1.2 Document organization................................................................................................................ 1
1.3 Basic physics of floating gate nonvolatile devices ...................................................................... 2
1.4 Introduction to floating gate memory arrays ............................................................................. 17
2. References......................................................................................................................................... 18
3. Definitions, abbreviations and acronyms, and symbols..................................................................... 19
3.1 Definitions................................................................................................................................. 19
3.2 Acronyms and abbreviations...................................................................................................... 26
3.3 Symbols .................................................................................................................................... 27
4. Basic floating gate FET types ............................................................................................................ 27
4.1 Background............................................................................................................................... 27
4.2 EPROM..................................................................................................................................... 28
4.3 E
2
PROM................................................................................................................................... 40
4.4 Flash memory cells .................................................................................................................... 44
5. Reliability considerations.................................................................................................................. 75
5.1 Background............................................................................................................................... 75
5.2 Failure rate components unique to floating gate devices........................................................... 75
5.3 MOS failure mechanisms........................................................................................................... 76
5.4 Effect of retention on failure rate............................................................................................... 76
5.5 Effect of endurance on failure rate............................................................................................. 78
5.6 Determination of composite failure rate .................................................................................... 79
5.7 Calculation of the composite failure rate ................................................................................... 79
5.8 Conclusion ................................................................................................................................ 81
6. Retention ........................................................................................................................................... 81
6.1 Background............................................................................................................................... 81
6.2 Concept of retention................................................................................................................... 82
6.3 Verification of retention............................................................................................................. 84
6.4 Discharge of capacitor by F-N tunneling................................................................................... 85
7. Endurance ......................................................................................................................................... 86
7.1 Background............................................................................................................................... 86
7.2 Endurance concept ..................................................................................................................... 86
7.3 Endurance rating objectives....................................................................................................... 89
7.4 Endurance verification approaches ............................................................................................ 90
8. Disturbs ............................................................................................................................................. 92
8.1 Introduction............................................................................................................................... 92
8.2 Basic disturb mechanisms.......................................................................................................... 92
vi
Copyright © 1999 IEEE. All rights reserved.
8.3 Program and erase disturbs ........................................................................................................ 96
8.4 Effects enhancing disturbs ......................................................................................................... 99
9. Testing methodology ....................................................................................................................... 100
9.1 Background............................................................................................................................. 100
9.2 Failure definition..................................................................................................................... 100
9.3 Methods of tests ....................................................................................................................... 101
9.4 Write conditions...................................................................................................................... 101
9.5 Power-supply sequence of EEPROMs..................................................................................... 103
9.6 Test patterns ............................................................................................................................. 103
9.7 Retention test conditions.......................................................................................................... 104
9.8 Endurance test conditions ........................................................................................................ 105
9.9 Appendix................................................................................................................................. 106
10. Ionizing radiation effects on floating gate memory ICs .................................................................. 108
10.1 Radiation effects background .................................................................................................. 108
10.2 Measurement of radiation effects............................................................................................. 110
10.3 Total dose tests......................................................................................................................... 111
10.4 Dose-rate tests.......................................................................................................................... 112
10.5 SEP tests.................................................................................................................................. 114
11. Other nonvolatile semiconductor structures .................................................................................... 115
11.1 Background............................................................................................................................. 115
11.2 Other semiconductor nonvolatile technologies........................................................................ 115
11.3 Non-memory applications of nonvolatile floating gate technology ........................................ 116
12. Bibliography ................................................................................................................................... 117

IEEE Standard Definitions and Characterization of Floating Gate Seimiconductor Arrays.rar

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发表于 2008-8-14 15:07:02 | 显示全部楼层
谢谢分享
发表于 2008-8-14 22:46:15 | 显示全部楼层
thanks!!!
发表于 2010-4-19 11:37:40 | 显示全部楼层
感謝分享
发表于 2010-6-18 15:43:45 | 显示全部楼层
good, thanks.
发表于 2010-6-20 16:41:52 | 显示全部楼层
感謝分享
发表于 2010-7-21 12:53:36 | 显示全部楼层
好东西啊,楼主,谢谢了
发表于 2010-7-21 19:18:55 | 显示全部楼层
thx for sharing
发表于 2010-7-27 18:17:25 | 显示全部楼层
kstha
发表于 2011-8-13 11:59:52 | 显示全部楼层
谢谢,学习一下
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