Is it necessary to resynchronize the reset here?

feb2008

in my design, PLL and clock divider are reset by rstn, clock divider is connected to PLL output, clk_a/clk_b/clk_c are generated by clock divider. Should I use rstn directly for modules clocked by clk_a/clk_b/clk_c, or resynchronize rstn with clk_a/clk_b/clk_c, producing rstn_a/rstn_b/rstn_c and use them for modules clocked by the corresponding clock? when should reset resynchronization be used?

[ 本帖最后由 feb2008 于 2008-5-30 13:57 编辑 ]