关于fifo的问题

xjtu_zhanglei

小弟最近写了一个fifo，写数据的时候没有问题，读数据的时候最后一个数据总是读不出来，读写指针和计数都正常，请各位高手看看：
//this fifo is used in I/O BUFFER.
//if MAC receive data ,WR active ,put data in fifo
//if need to transfer data from fifo to SRAM,RD active
`define WIDTH  8         //DATA WIDTH
`define DEPTH  1024      //THE MAX DATA CAPACITY
`define COUNTERADDR  16  //THE NUMBER OF ADDRESS LINES
module FIFO(clk,rst,clear,datain,WR,RD,
       dataout,full,empty,lastdata,firstdata,counter,rdpointer,wrpointer);
input clk;
input rst;
input clear;
input WR,RD;
input[(`WIDTH-1):0] datain;

output[(`WIDTH-1):0] dataout;
output full;          //indicated that the fifo is full
output empty;         //indicated that the fifo is empty
output lastdata;      //indicated that the fifo has space for only one data ;
output firstdata;     //indicated that the fifo has only one data in
output[`COUNTERADDR:0] counter;
output[(`COUNTERADDR-1):0] rdpointer,wrpointer;
wire [(`WIDTH-1):0] dataout;
reg full;
reg empty;
reg lastdata;
reg firstdata;
reg [`COUNTERADDR:0] counter;           //indicated that number of data in fifo
reg [(`COUNTERADDR-1):0] rdpointer;     //indicated the current read pointer,the address that read in
reg [(`COUNTERADDR-1):0] wrpointer;     //indicated the current write pointer,the address that write in


wire[(`WIDTH-1):0] memdatain;
wire[(`WIDTH-1):0] memdataout;
//wire MEMRD=RD;
//wire MEMWR=WR;
assign dataout=memdataout;
assign memdatain=datain;  
//MEM_BLOCK  FIFO_MEM_BLOCK(.clk(clk),.WR(MEMWR),.WADDR(wrponiter),.RD(MEMRD),.RADDR(rdpointer),
  //                         .datain(memdatain),.dataout(memdataout)) ;
  
  
  
  // describe repointer and wrpointer                        
  [email=always@(posedge]always@(posedge[/email] clk or negedge rst) begin
  if(!rst) begin
  counter<=0;                        
  rdpointer<=0;
  wrpointer<=0;
  end
  else if(clear) begin
      counter<=0;
      rdpointer<=0;
      wrpointer<=0;
  end
  
  else begin
      if(WR&&!full)     //WR and RD and all the flags are active available
      wrpointer<=wrpointer+1;
      if(RD&&!empty)
      rdpointer<=rdpointer+1;
      if(!WR&&RD&&!empty)
      counter<=counter-1;
      else if(WR&&!RD&&!full)
      counter<=counter+1;
  end
end   

//describe empty flag

[email=always@(posedge]always@(posedge[/email] clk or negedge rst) begin
     if(!rst) //begin
         empty<=1'b1;
         else        begin
         if(!clear) begin
             if((empty==1)&&WR)
             empty<=1'b0;
             else if((firstdata==1)&&!WR&&RD)
             empty<=1'b1;
             else if(counter==17'b0)
            empty<=1'b1;
            else empty<=1'b0;
         end
         else
         empty<=1'b1;
     end
end  

//describe firstdata flag

[email=always@(posedge]always@(posedge[/email] clk or negedge rst) begin
     if(!rst)
     firstdata<=1'b0;  
     else  begin
         if(!clear) begin
             if((empty==1'b1)&&WR&&!RD)
             firstdata<=1'b1;
             else if((counter==17'b0_0000000000000010)&&RD)
             firstdata<=1'b1;
             else if((firstdata==1'b1)&&WR)
             firstdata<=1'b0;
             else if((firstdata==1'b1)&&RD)
             firstdata<=1'b0;
         end
         else
         firstdata<=1'b0;
     end
end
//describe lastdata flag

[email=always@(posedge]always@(posedge[/email] clk or negedge rst) begin
     if(!rst)
     lastdata<=1'b0;
     else begin
         if(!clear) begin
             if((full==1)&&RD)
             lastdata<=1;
             else if(counter==(`DEPTH-2)&&RD&&!WR)
             lastdata<=1'b1;
             else if((lastdata==1'b1)&&(RD^WR))
              lastdata<=1'b0;
        end   
    else lastdata<=1'b0;
  end
end
//describe full flag
[email=always@(posedge]always@(posedge[/email] clk or negedge rst) begin
if(!rst)  
full<=1'b0;
else begin
     if(!clear) begin
                if((lastdata==1'b1)&&WR&&!RD)
                  full<=1'b1;
                  else if((full==1'b1)&&RD)
                  full<=1'b0;
              end
      else full<=1'b0;
     end
  end        
               
MEM_BLOCK  FIFO_MEM_BLOCK(.clk(clk),.WR(WR),.WADDR(wrpointer),.RD(RD),.RADDR(rdpointer),
                            .datain(memdatain),.dataout(memdataout)) ;


endmodule


// this module is describe the memory that used in FIFO and in SRAM
`define WIDTH  8         //DATA WIDTH
`define DEPTH  1024      //THE MAX DATA CAPACITY
`define COUNTERADDR  16  //THE NUMBER OF ADDRESS LINES
module MEM_BLOCK(clk,WR,WADDR,RD,RADDR,datain,dataout);
    input clk;
    input WR,RD;
    input[(`WIDTH-1):0] datain;
    input[(`COUNTERADDR-1):0] WADDR;
    input[(`COUNTERADDR-1):0] RADDR;
   
    output[(`WIDTH-1):0] dataout;
   
    wire[(`WIDTH-1):0] dataout;
   
    reg[(`WIDTH-1):0] MEM[0`DEPTH-1)] ;
   
    assign dataout=(RD) ? MEM[RADDR]:16'bz;
    [email=always@(posedge]always@(posedge[/email] clk)
    begin
    if(WR)
    MEM[WADDR]<=datain;
   end
   
   endmodule