Systemverilog Standard Gotchas

neocent · 发表于 2008-4-17 12:51:04

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Table of Contents
1.0 Introduction ............................................................................................................................3
2.0 Declaration gotchas ................................................................................................................4
2.1 Case sensitivity ............................................................................................................4
2.2 Implicit net declarations ............................................................................................... 5
2.3 Escaped identifiers in hierarchy paths  ......................................................................... 6
2.4 Verification of dynamic data  ....................................................................................... 7
2.5 Variables declared in unnamed blocks  ........................................................................ 8
2.6 Hierarchical references to declarations imported from packages  ................................ 8
2.7 Variables with no hierarchy path are not dumped to VCD files .................................. 9
2.8 Shared variables in modules  ........................................................................................ 9
2.9 Shared variables in interfaces, packages, and $unit ................................................... 10
2.10 Shared variables in tasks and functions  ..................................................................... 10
2.11 Importing enumerated types from packages  .............................................................. 11
2.12 Importing from multiple packages ............................................................................. 11
3.0 Two-state gotchas ................................................................................................................12
3.1 Resetting 2-state models ............................................................................................ 12
3.2 Locked state machines  ............................................................................................... 13
3.3 Hidden design problems ............................................................................................ 15
3.4 Out-of-bounds indication lost  .................................................................................... 16
4.0 Literal number gotchas  ........................................................................................................16
4.1 Signed versus unsigned literal integers ...................................................................... 17
4.2 Default base of literal integers  ................................................................................... 17
4.3 Size mismatch in literal integers  ................................................................................ 18
4.4 Literal number size mismatch in assignments  ........................................................... 20
4.5 Literal number Z and X extension backward compatibility  ...................................... 21
4.6 Filling vectors  ............................................................................................................ 22
4.7 Passing real (floating point) numbers through ports .................................................. 22
4.8 Port connection rules ................................................................................................. 23
4.9 Back-driven input ports  ............................................................................................. 26
5.0 Operator gotchas ..................................................................................................................27
5.1 Self-determined operations versus context-determined operations  ........................... 27
5.2 Operation size and sign extension in assignment statements  .................................... 30
5.3 Signed arithmetic ....................................................................................................... 32
5.4 Bit select and part select operations ........................................................................... 34
5.5 Increment, decrement and assignment operations  ..................................................... 35
5.6 Pre-increment versus post-increment operations  ....................................................... 35
5.7 Operations that modify the same variable multiple times in an assignment  ............. 36
5.8 Operator evaluation short circuiting .......................................................................... 37
6.0 Programming gotchas  ..........................................................................................................38
6.1 Assignments in expressions ....................................................................................... 38
6.2 Procedural block activation  ....................................................................................... 38
6.3 Combinational logic sensitivity lists  .......................................................................... 40
6.4 Arrays in sensitivity lists ............................................................................................ 41
6.5 Vectors in sequential logic sensitivity lists  ................................................................ 42
6.6 Operations in sensitivity lists  ..................................................................................... 43
6.7 Sequential blocks with begin...end groups  ............................................................... 44
6.8 Sequential blocks with partial resets .......................................................................... 45
6.9 Blocking assignments in sequential procedural blocks  ............................................. 45
6.10 Evaluation of true/false on 4-state values  .................................................................. 46
6.11 Mixing up the not operator ( ! ) and invert operator ( ~ )  .......................................... 47
6.12 Nested if...else blocks ................................................................................................ 47
6.13 Casez/casex masks in case expressions  ..................................................................... 48
6.14 Incomplete or redundant decisions  ............................................................................ 49
6.15 Out-of-bounds assignments to enumerated types ...................................................... 50
6.16 Statements that hide design problems ........................................................................ 51
6.17 Simulation versus synthesis mismatches ................................................................... 53
7.0 Testbench gotchas  ................................................................................................................53
7.1 Multiple levels of the same virtual method  ............................................................... 53
7.2 Event trigger race conditions ..................................................................................... 54
7.3 Using semaphores for synchronization  ...................................................................... 56
7.4 Using mailboxes for synchronization ........................................................................ 58
7.5 Coverage reporting  .................................................................................................... 59
7.6 $unit declarations ....................................................................................................... 60
7.7 Compiling $unit  ......................................................................................................... 61
8.0 References ............................................................................................................................62
9.0 About the authors .................................................................................................................62

neocent · 发表于 2008-4-17 12:52:22

Table of Contents
1.0 Introduction ............................................................................................................................3
2.0 Design modeling gotchas .......................................................................................................4
2.1 Overlapped decision statements ................................................................................... 4
2.2 Inappropriate use of unique case statements ................................................................ 5
2.3 Simulation versus synthesis mismatch in intended combinational logic ..................... 7
2.4 Nonblocking assignments in combinational logic with a feedback loops  ................... 9
2.5 Default of 1-bit internal nets  ...................................................................................... 10
2.6 Port direction coercion ............................................................................................... 12
3.0 General programming gotchas .............................................................................................13
3.1 Compile errors with clocking blocks  ......................................................................... 13
3.2 Misplaced semicolons after end or join statement groups  ......................................... 14
3.3 Misplaced semicolons after decision statements  ....................................................... 14
3.4 Misplaced semicolons in for-loops  ............................................................................ 16
3.5 Infinite for-loops ........................................................................................................ 17
3.6 Locked simulation due to concurrent for-loops  ......................................................... 17
3.7 Referencing for-loop control variables outside of the loop  ....................................... 19
3.8 Summing a subset of value in an array returns an incorrect value  ............................ 19
3.9 Task/function arguments with default values  ............................................................ 20
3.10 Static tasks and functions are not re-entrant .............................................................. 21
3.11 Compile error from a local variable declaration  ........................................................ 23
4.0 Object Oriented Programming (OOP) gotchas  ....................................................................23
4.1 Programming statements in a class get compilation errors ........................................ 23
4.2 Compile errors when using interfaces with classes  ................................................... 25
4.3 Objects in mailbox have the same values .................................................................. 26
4.4 Passing object handles to methods using input versus ref arguments  ....................... 26
4.5 Creating an array of objects  ....................................................................................... 27
5.0 Constrained random verification gotchas  ............................................................................28
5.1 Some object variables are not getting randomized  .................................................... 28
5.2 Boolean constraints on more than two random variables  .......................................... 29
5.3 Undetected randomization failures ............................................................................ 30
5.4 Unwanted negative numbers in random values  ......................................................... 31
6.0 SystemVerilog coverage gotchas  .........................................................................................32
6.1 Coverage is always reported as 0% for a cover group ............................................... 32
6.2 The coverage report lumps all instances together ...................................................... 33
6.3 Covergroup argument directions are sticky  ............................................................... 34
7.0 SVA gotchas  ........................................................................................................................35
7.1 Assertion pass statements execute with a vacuous success  ....................................... 35
7.2 Concurrent assertions in procedural blocks ............................................................... 36
7.3 Mismatch in assert...else statements .......................................................................... 37
8.0 Tool compatibility gotchas  ..................................................................................................38
8.1 Default simulation time units and precision  .............................................................. 38
8.2 Package chaining  ....................................................................................................... 39
8.3 Loading memories modeled with always_latch ......................................................... 40
8.4 Non-standard keywords ............................................................................................. 42
8.5 Array literals versus concatenations .......................................................................... 43
8.6 Module ports that pass floating point values (real types)  .......................................... 44
9.0 Corrections to the first gotchas paper  ..................................................................................44
10.0 References and resources  .....................................................................................................45
11.0 About the authors  .................................................................................................................46

austin_lin · 发表于 2008-4-17 13:30:15

These are the papers that Sutherland submitted at SNUG. Interesting to read - though it would be nice if someone can post/share another SystemVerilog Gotchas book from the same author. Thanks!