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I INTRODUCTION................................................................................................ 1
II FUNDAMENTALS OF VGA DESIGN............................................................... 5
A. Gain and Bandwidth Specifications ............................................................... 5
1. Cascoding................................................................................................ 6
2. Gain boosting in differential amplifiers with diode connected loads ......... 8
3. Capacitive neutralization to increase bandwidth..................................... 10
B. Group Delay................................................................................................ 12
C. Common Mode Rejection Ratio (CMRR) and Power Supply Rejection
Ratio (PSRR)............................................................................................... 13
1. Small signal characteristics of differential amplifiers ............................. 13
2. Common mode feedback circuit............................................................. 16
D. Noise-to-Power Ratio .................................................................................. 18
E. DC Offset .................................................................................................... 20
1. Systematic offset voltage ....................................................................... 20
2. Random offset voltage ........................................................................... 22
III DESIGN OF THE VARIABLE GAIN AMPLIFIER.......................................... 23
A. Blocks of the VGA...................................................................................... 24
1. Digital-to-analog converter .................................................................... 24
2. Exponential voltage generator................................................................ 26
3. VGA core – stages 1 and 2..................................................................... 34
4. VGA core – stage 3................................................................................ 46
5. DC offset cancellation circuit................................................................. 48
6. Common mode feedback circuit............................................................. 58
7. Bias generator........................................................................................ 66
B. Layout….. ................................................................................................... 67
1. Multi-finger transistors .......................................................................... 67
2. Symmetry .............................................................................................. 68
3. Voltage and current routing.................................................................... 68
4. Passive devices ...................................................................................... 70
vi
CHAPTER Page
IV SIMULATION RESULTS................................................................................. 72
A. Schematic Simulations................................................................................. 72
B. Post-Layout Simulations.............................................................................. 81
V CONCLUSION.................................................................................................. 89 |
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发表于 2008-4-16 21:43:22
